10AS066H3F34I2LG vs 10AS057H3F34I2LG Vergleich
Detaillierter Direktvergleich von 10AS066H3F34I2LG von Altera und 10AS057H3F34I2LG von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
10AS057H3F34I2LG - Arria 10 SX SoC FPGA, 570K LE, Dual ARM Cortex-A9 | Intel
10AS057H3F34I2LG ✓ AktivSpezifikationsvergleich
| Parameter | 10AS066H3F34I2LG | 10AS057H3F34I2LG |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $2.950,00 |
| Product Type | System-on-chip FPGA | — |
| FPGA Family | Arria 10 SX | — |
| Logic Elements | 660000 | 570 K |
| Processor Subsystem | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum Stated Frequency | 1.5 GHz | — |
| I/O Count | 492 I/O | — |
| Technology | 20 nm | — |
| Core Voltage Snippet | 0.9 V | — |
| Cell Count | 660000 cells | — |
| Package Pin Count | 1152 pins | — |
| Package Type | FCBGA | — |
| Package Dimensions | 35 mm x 35 mm | — |
| Terminal Form | Ball | — |
| Montageart | Surface Mount | Surface Mount |
| Temperature Grade | Industrial | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Family | — | Arria 10 SX SoC FPGA |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Core Frequency | — | 1.5 GHz |
| Gehäuse | — | 1152-ball FCBGA (F34, 35x35 mm) |
| Process Node | — | 20 nm |
| Operating Temperature (Industrial) | — | -40 C to +100 C (junction) |
| Speed Grade | — | I2 (mid-speed, industrial) |
| User I/O | — | 492 (per Heisener listing) |
| Transceivers | — | Up to 16.7 Gbps (per Arria 10 family) |
| Hard Memory Controllers | — | DDR3/DDR4 with ECC |
| MSL-Level | — | [DATA_NEEDED: MSL level] |
| Supply Voltage (Core) | — | [DATA_NEEDED: core VCC] |