10AX090S4F45I3LG vs 10AX090S4F45E3LG Vergleich
Detaillierter Direktvergleich von 10AX090S4F45I3LG von Intel und 10AX090S4F45E3LG von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | 10AX090S4F45I3LG | 10AX090S4F45E3LG |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $6.050,00 | $4.582,63 |
| Family | Arria 10 GX | Arria 10 GX (10AX090) |
| Logic Elements | 900,000 | — |
| Adaptive Logic Modules (ALMs) | [DATA_NEEDED: ALM count] | — |
| Embedded Memory (bits) | 59,234,304 (approx. 59 Mbit) | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | [DATA_NEEDED: DSP slice count] |
| User I/Os | 624 | — |
| Gehäuse | 1932-ball FCBGA (45 x 45 mm) | 1932-ball FCBGA (F45, 45 mm) |
| Process Technology | 20 nm | — |
| Transceivers | Up to 24 channels | Up to 28.05 Gbps backplane-capable |
| Transceiver Data Rate | Up to 17.4 Gbps per channel | — |
| Hard Memory Controller | Yes (DDR3/DDR4, LPDDR2, QDR IV) | — |
| PCIe Hard IP | PCIe Gen3 x8 (hard IP block) | — |
| Betriebstemperatur | -40C to +100C (Industrial) | — |
| Versorgungsspannung | [DATA_NEEDED: VCCINT/VCCIO nominal] | — |
| RoHS-Status | Compliant | Compliant |
| Montageart | Surface Mount (BGA) | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Speed Grade | -3 (faster speed grade) | -3 (enhanced, E3) |
| Series | — | Arria 10 GX |
| Logic Elements (LE) | — | 900,000 |
| Adaptive Logic Modules (ALM) | — | [DATA_NEEDED: ALM count] |
| Embedded Memory | — | 59,234,304 bits (~7.4 Mbytes) |
| Maximum User I/O Pins | — | 624 |
| Ball Pitch | — | 1.0 mm |
| Temperature Grade | — | Industrial (LG suffix) |
| Lead-Free / Halogen-Free | — | Yes (LG suffix indicates lead-free, no heat spreader) |
| Process Node | — | 20 nm TSMC |
| PLL Count | — | [DATA_NEEDED: PLL count] |
| Configuration | — | FPGA - Field Programmable Gate Array |