10AX090U4F45E3LG vs 10AX090U3F45E2LG Vergleich
Detaillierter Direktvergleich von 10AX090U4F45E3LG von Intel und 10AX090U3F45E2LG von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | 10AX090U4F45E3LG | 10AX090U3F45E2LG |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7.147,87 | $6.900,00 |
| Manufacturer | Altera | — |
| Current Brand | Intel | — |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Family | Arria 10 GX | — |
| Logic Elements | 900000 | — |
| User I/O | 480 | — |
| Embedded Memory | 59234304 bit | — |
| Gehäuse | 1932-BBGA, FCBGA | 1932-BBGA, FCBGA |
| Terminal Count | 1932 | — |
| Terminal Form | Ball | — |
| Package Code | BGA | — |
| Package Shape | Square | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Transceiver Count | [DATA_NEEDED: transceiver count] | — |
| Maximum Transceiver Data Rate | [DATA_NEEDED: maximum transceiver data rate] | [DATA_NEEDED: exact Gbps] |
| DSP Block Count | [DATA_NEEDED: DSP block count] | — |
| Temperature Grade | [DATA_NEEDED: temperature grade] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Speed Grade | [DATA_NEEDED: speed grade] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Compliant |
| Series | — | Arria 10 GX |
| Logic Elements (LE) | — | 900,000 |
| Number of Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Embedded Memory Bits | — | 59,234,304 bits |
| Number of Transceivers | — | 48 transceiver macro channels (480 I/O references) |
| Hard Memory Controllers | — | Yes - DDR4, DDR3, QDR IV, RLDRAM 3 with hardened PHY |
| Hard PCIe Controllers | — | PCIe Gen3 x8 |
| Hard Ethernet MACs | — | 10GbE and 100GbE MACs |
| Adaptive Logic Modules (ALMs) | — | [DATA_NEEDED: ALM count] |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Number of I/O Banks | — | [DATA_NEEDED: bank count] |
| Maximum User I/O Pins | — | 480 (per DigiKey listing) |
| Package Pin Pitch | — | [DATA_NEEDED: pitch] |
| Operating Temperature Grade | — | OTHER / Extended (per Partstack listing) |
| Process Technology | — | 20nm TSMC |
| Configuration Method | — | Serial (active/passive) and parallel via Quartus Prime |
| Development Tool | — | Intel Quartus Prime |