10CL006ZE144I8G vs 10CL006YE144A7G Vergleich
Detaillierter Direktvergleich von 10CL006ZE144I8G von Altera und 10CL006YE144A7G von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | 10CL006ZE144I8G | 10CL006YE144A7G |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $35,88 | $17,40 |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Product Family | Cyclone 10 LP | — |
| Logic Cell Count | 6,272 cells | — |
| Embedded Memory | 276,480 bits | 276,480 bits (270 Kbits) |
| User I/O Count | 88 I/O | — |
| Package Type | 144-pin LQFP with exposed pad | — |
| Montageart | Surface Mount | Surface Mount |
| Programmable Logic Technology | FPGA | — |
| Configuration Storage Technology | [DATA_NEEDED: configuration memory technology] | — |
| Core Supply Voltage | [DATA_NEEDED: core supply voltage] | — |
| I/O Supply Voltage | [DATA_NEEDED: I/O supply voltage] | — |
| Betriebstemperaturbereich | [DATA_NEEDED: operating temperature range] | — |
| Speed Grade | [DATA_NEEDED: speed grade] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Family | — | Cyclone 10 LP |
| Density (Logic Elements) | — | 6,272 LEs |
| Embedded 18x18 Multipliers | — | 15 |
| General-Purpose I/Os | — | 88 |
| User I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| PLLs | — | 2 |
| Global Clock Networks | — | [DATA_NEEDED: number of global clocks] |
| Configuration Memory | — | Internal SRAM, externally loaded |
| Gehäuse | — | 144-LQFP Exposed Pad (E144) |
| Betriebstemperatur | — | -40C to +85C (Industrial) |
| Supply Voltage (Core) | — | [DATA_NEEDED: VCCINT nominal] |
| Supply Voltage (I/O) | — | [DATA_NEEDED: VCCIO range] |
| Process Node | — | Low-power CMOS |
| MSL-Level | — | 3 (per JEDEC J-STD-020) |