10CL055YF484C6G vs 10CL055YU484C6G Vergleich
Detaillierter Direktvergleich von 10CL055YF484C6G von Intel und 10CL055YU484C6G von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | 10CL055YF484C6G | 10CL055YU484C6G |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $112,40 | $24,38 |
| Family | Cyclone 10 LP | Cyclone 10 LP |
| Logic Elements (LE) | 55,856 | 55,856 |
| Adaptive Logic Modules (ALM) | [DATA_NEEDED: ALM count] | — |
| Embedded Memory (bits) | 2,396,160 | — |
| Embedded Memory Blocks | M9K | — |
| Embedded 18x18 Multipliers | 156 | 156 |
| General-Purpose PLLs | 4 | — |
| Maximum User I/O | 321 | — |
| Gehäuse | 484-ball FBGA (F484) | 484-pin UBGA (19 mm x 19 mm) |
| Speed Grade | -6 | 6 (commercial, slowest in family) |
| Betriebstemperatur | 0 °C to +85 °C (commercial) | 0 C to +85 C (commercial, C suffix) |
| Core Voltage | 1.2 V | 1.0 V (typical) |
| I/O Standards Supported | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V LVCMOS/LVTTL; LVDS | — |
| Configuration Modes | JTAG, Active Serial (AS), Passive Serial (PS), Fast Passive Parallel (FPP) | Active Serial (AS), Passive Serial (PS), JTAG |
| Process Technology | Low-power CMOS (TSMC) | TSMC 60 nm low-power |
| RoHS-Status | Compliant | Compliant |
| Montageart | Surface Mount | Surface Mount |
| MSL-Level | 3 (per JEDEC J-STD-020) | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Embedded Memory Bits | — | 2,396,160 bits (approximately 2.5 Mb) |
| Maximum User I/Os | — | 321 |
| PLLs | — | 4 |
| Global Clocks | — | 20 |
| I/O Voltage Standards | — | LVDS, LVTTL, LVCMOS, SSTL, HSTL (1.2 V to 3.3 V) |
| Lead-Free / Halogen-Free | — | Yes / [DATA_NEEDED: halogen-free status] |
| Transceivers | — | None (Cyclone 10 LP family does not include SERDES) |
| Hard Memory Controller | — | Yes (DDR/DDR2/DDR3/LPDDR2 via soft IP) |