10CL055YU484C6G vs 10CL055YF484C6G Vergleich

Detaillierter Direktvergleich von 10CL055YU484C6G von Altera und 10CL055YF484C6G von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter 10CL055YU484C6G 10CL055YF484C6G
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Aktiv Aktiv
Lagerstatus In Stock In Stock
Stückpreis (USD) $24,38 $112,40
Family Cyclone 10 LP Cyclone 10 LP
Logic Elements (LE) 55,856 55,856
Embedded Memory Bits 2,396,160 bits (approximately 2.5 Mb) —
Maximum User I/Os 321 —
Embedded 18x18 Multipliers 156 156
PLLs 4 —
Global Clocks 20 —
Core Voltage 1.0 V (typical) 1.2 V
I/O Voltage Standards LVDS, LVTTL, LVCMOS, SSTL, HSTL (1.2 V to 3.3 V) —
Speed Grade 6 (commercial, slowest in family) -6
Gehäuse 484-pin UBGA (19 mm x 19 mm) 484-ball FBGA (F484)
Process Technology TSMC 60 nm low-power Low-power CMOS (TSMC)
Betriebstemperatur 0 C to +85 C (commercial, C suffix) 0 °C to +85 °C (commercial)
Montageart Surface Mount Surface Mount
MSL-Level [DATA_NEEDED: MSL level per JEDEC J-STD-020] 3 (per JEDEC J-STD-020)
RoHS-Status Compliant Compliant
Lead-Free / Halogen-Free Yes / [DATA_NEEDED: halogen-free status] —
Configuration Modes Active Serial (AS), Passive Serial (PS), JTAG JTAG, Active Serial (AS), Passive Serial (PS), Fast Passive Parallel (FPP)
Transceivers None (Cyclone 10 LP family does not include SERDES) —
Hard Memory Controller Yes (DDR/DDR2/DDR3/LPDDR2 via soft IP) —
Adaptive Logic Modules (ALM) — [DATA_NEEDED: ALM count]
Embedded Memory (bits) — 2,396,160
Embedded Memory Blocks — M9K
General-Purpose PLLs — 4
Maximum User I/O — 321
I/O Standards Supported — 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V LVCMOS/LVTTL; LVDS

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