5CSEBA2U19C8N vs 5CSEBA2U19I7N Vergleich
Detaillierter Direktvergleich von 5CSEBA2U19C8N von Altera und 5CSEBA2U19I7N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | 5CSEBA2U19C8N | 5CSEBA2U19I7N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $52,40 | $445,65 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Series | 5CSEA2 | — |
| Device Variant | 5CSEBA2 (25K logic elements, dual ARM Cortex-A9) | — |
| Core Architecture | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 600 MHz | — |
| FPGA Logic Elements | 25,000 | — |
| Embedded Memory (M10K) | 1,400 Kb (typical for 25K LE variant) | — |
| DSP Blocks | Variable-precision DSP | — |
| Process Technology | 28 nm low-power | 28 nm TSMC low-power |
| Core Supply Voltage | 1.1 V | — |
| Memory Controller Support | DDR2, DDR3, LPDDR2 | — |
| High-Speed Transceivers | Present (Cyclone V SE family feature) | — |
| PLLs | Multiple (per Cyclone V SE device handbook) | — |
| Gehäuse | 484-pin UBGА (19x19 mm) | 484-UBGA (19x19 mm) |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Betriebstemperatur | 0C to +85C (commercial) | -40C to +100C (Industrial) |
| MSL-Level | 3 (per JEDEC J-STD-020, assumed for 484-BGA) | — |
| RoHS-Status | Compliant | Compliant |
| Logic Elements | — | 25K |
| HPS | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Clock Frequency | — | 800 MHz |
| Embedded Memory | — | 1,400 Kbits |
| DSP Blocks (18x18 Multipliers) | — | 66 |
| User I/O Pins | — | 145 |
| LVDS Support | — | Up to 1.25 Gbps |
| Voltage - Input (Max) | — | 1.1 V core |
| Peripherals | — | USB 2.0 OTG, Gigabit Ethernet, CAN, UART, SPI, I2C, NAND/NOR flash controllers |
| HPS-FPGA Interconnect | — | AXI bridges (3 master / 3 slave), FPGA-to-HPS SDRAM, DMA |