5CSEBA4U19C6N vs 5CSEBA4U19C8N Vergleich
Detaillierter Direktvergleich von 5CSEBA4U19C6N von Intel und 5CSEBA4U19C8N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
5CSEBA4U19C6N - Cyclone V SE SoC FPGA, 40K LE, Dual ARM Cortex-A9 | Intel
5CSEBA4U19C6N ✓ AktivIntel
5CSEBA4U19C8N - Cyclone V SE SoC FPGA, 40K LE, Dual ARM Cortex-A9 | Intel
5CSEBA4U19C8N ✓ AktivSpezifikationsvergleich
| Parameter | 5CSEBA4U19C6N | 5CSEBA4U19C8N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $74,50 | $54,75 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 40,000 (40K LE) | 40K |
| Hard Processor System (HPS) | Dual-core ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum HPS Clock Frequency | 925 MHz | — |
| Gehäuse | 484-pin UFBGA / UBGA (19x19 mm) | 484-UBGA (19x19 mm) |
| FPGA User I/O | 161 (per Altera product page) | — |
| Process Technology | TSMC 28 nm low-power | TSMC 28nm low-power |
| Memory Controller | Hard controller for DDR2 / DDR3 / LPDDR2 | — |
| DSP Blocks | Variable-precision DSP blocks (18x18 multipliers) | [DATA_NEEDED: number of DSP blocks] |
| Embedded Memory | M10K memory blocks | — |
| Encryption Support | AES encryption (per LCSC listing) | — |
| Error Detection | SEU error detection and correction support | — |
| Betriebstemperatur | 0C to +85C (commercial grade) | 0C to +85C (commercial) |
| Montageart | Surface Mount (BGA) | Surface Mount (BGA) |
| RoHS-Status | Compliant | Compliant |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 600 MHz |
| FPGA Fabric Speed Grade | — | -8 |
| User I/O Count | — | 161 |
| Lead-Free | — | Yes |
| MSL-Level | — | 3 (168 hours) |
| Supply Voltage (Core) | — | [DATA_NEEDED: VCC core voltage] |
| Embedded Memory (M10K) | — | [DATA_NEEDED: M10K block count] |
| Transceivers | — | None (SE variant - no high-speed transceivers) |
| Configuration Method | — | Serial (EPCS) and Parallel |