5CSEBA4U23A7N vs 5CSEBA2U23A7N Vergleich
Detaillierter Direktvergleich von 5CSEBA4U23A7N von Altera und 5CSEBA2U23A7N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | 5CSEBA4U23A7N | 5CSEBA2U23A7N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $185,00 | $99,50 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Device Variant | 5CSEA4 | — |
| Logic Elements | 40 K | 25,000 LE |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 700 MHz | 700 MHz |
| Gehäuse | 672-pin UBGA (U23, 23x23 mm) | 672-UBGA (23x23 mm) |
| Process Node | 28 nm low power | — |
| DSP Blocks | Variable-precision DSP blocks (Cyclone V SE family feature) | Variable-precision DSP (count [DATA_NEEDED: exact count]) |
| Embedded Memory | M10K memory blocks (family feature) | M10K blocks (count [DATA_NEEDED: exact M10K/M20K count]) |
| Speed Grade | 7 | 7 |
| Betriebstemperatur | [DATA_NEEDED: industrial temp range explicit value] | — |
| Family Maximum Logic Elements | Up to 301 K LE | — |
| Montageart | Surface Mount (BGA) | Surface Mount (BGA) |
| RoHS-Status | Compliant | Compliant (per ampheo listing) |
| MSL-Level | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL level] |
| HPS Peripherals | Gigabit Ethernet, USB 2.0, SATA, UART, SPI, I2C, CAN | — |
| FPGA-HPS Interface | ARM AMBA AXI coherence fabric | — |
| MPN Code | — | 5CSEBA2U23A7N (Cyclone V SE A2, U23 package) |
| Hard Processor System (HPS) | — | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| Process Technology | — | 28 nm low-power |
| User I/O | — | 188 |
| Temperature Grade | — | A (Commercial, 0C to +85C) [DATA_NEEDED: exact junction range] |
| Operating Voltage (Core) | — | 1.1 V (typical FPGA core, multi-rail HPS) |
| Configuration Scheme | — | HPS-boot of FPGA fabric via configuration QSPI |
| PLLs | — | Fractional PLLs (count [DATA_NEEDED: exact PLL count]) |