5M1270ZT144C5N vs 5M240ZT144C4N Vergleich
Detaillierter Direktvergleich von 5M1270ZT144C5N von Altera und 5M240ZT144C4N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ AktivSpezifikationsvergleich
| Parameter | 5M1270ZT144C5N | 5M240ZT144C4N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $12,45 | $5,78 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Series | MAX V | — |
| Logic Elements | 1270 | — |
| Macrocells | 980 | — |
| User I/Os | 114 | — |
| Maximum Internal Frequency | 118.3 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 6.2 ns | — |
| Internal Frequency (typical) | 201 MHz | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Configuration Memory | Flash (non-volatile, in-system programmable) | On-chip flash (non-volatile, instant-on) |
| VCCINT (Core Supply) | 1.71 V to 1.89 V | — |
| VCCIO (I/O Supply, per bank) | 1.2 V to 3.3 V | — |
| Number of I/O Banks | 4 | — |
| Supported I/O Standards | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins | — |
| JTAG Interface | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) | — |
| Programming Interface | JTAG in-system programmable (Altera Quartus II) | — |
| Program/Erase Cycles | Up to 100,000 | — |
| Gehäuse | TQFP-144 (22 x 22 mm, 0.5 mm pitch) | 144-pin TQFP (T144) |
| Montageart | Surface Mount | Surface Mount (TQFP) |
| Betriebstemperatur | 0 C to +85 C (commercial grade) | — |
| RoHS-Status | Compliant | Compliant |
| Family | — | MAX V |
| Logic Elements (Macro Cells) | — | 192 |
| Maximum User I/O Pins | — | [DATA_NEEDED: max user I/O for 144 TQFP variant] |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Supply Voltage (VCCIO) | — | 1.5 V to 3.3 V (multi-volt) |
| Maximum Operating Frequency (fMAX) | — | 184.1 MHz |
| Pin-to-Pin Delay (tPD) | — | 4.5 ns (C4 speed grade) |
| Speed Grade | — | C4 (commercial, fastest) |
| Betriebstemperaturbereich | — | 0 C to +85 C (commercial) |
| JTAG Support | — | IEEE 1149.1 boundary-scan + programming |
| Lead-Free | — | Yes |
| MSL-Level | — | 3 (168 hours) |
| Process Node | — | [DATA_NEEDED: process node] |