5M160ZE64C5N vs 5M160ZM68C5N Vergleich
Detaillierter Direktvergleich von 5M160ZE64C5N von Altera und 5M160ZM68C5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | 5M160ZE64C5N | 5M160ZM68C5N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,95 | $3,12 |
| Series | MAX V | 5M160Z |
| Device Family | MAX V (5M160Z) | — |
| Logic Elements (LE) | 160 | — |
| Macrocells | 128 | 128 |
| User I/O Pins | 54 | — |
| Maximum Operating Frequency (fMAX) | 118.3 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 1.4 ns (per datasheet) | — |
| Configuration Memory | Non-volatile Flash | Non-volatile flash (instant-on, no boot PROM required) |
| Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| User Flash Memory | 8 Kbits | 8 Kbits |
| Gehäuse | 64-pin EQFP (E64) with exposed pad | — |
| Montageart | Surface Mount | — |
| Betriebstemperatur | 0°C to +85°C (commercial) | — |
| Programming Interface | JTAG (IEEE 1149.1) / In-system | JTAG (IEEE Std. 1149.1), in-system programmable |
| RoHS-Status | Compliant | Compliant |
| MSL-Level | 3 | [DATA_NEEDED: MSL level] |
| Family | — | MAX V CPLD |
| Logic Elements (typical) | — | 160 |
| Maximum Operating Frequency | — | 118.3 MHz |
| Pin-to-Pin Logic Delay | — | 7.5 ns |
| Number of Logic Array Blocks (LABs) | — | 4 |
| Core Supply Voltage | — | 1.8 V |
| I/O Standards Supported | — | LVTTL, LVCMOS 1.5/1.8/2.5/3.3 V |
| Package Type | — | 68-ball Micro FineLine BGA (MBGA) |
| Betriebstemperaturbereich | — | 0C to +85C (commercial) |
| Internal Oscillator | — | Yes (on-chip) |
| Lead-Free | — | Yes |