5M240ZM68I5N vs 5M240ZM68C5N Vergleich
Detaillierter Direktvergleich von 5M240ZM68I5N von Intel und 5M240ZM68C5N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | 5M240ZM68I5N | 5M240ZM68C5N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1,25 | $9,05 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Series | MAX V | MAX V |
| Logic Elements | 240 | 240 |
| Number of Macrocells | 192 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Configuration Memory | Nonvolatile Flash | — |
| Package Type | TFBGA-68 | — |
| Number of Terminals | 68 (ball) | — |
| Package Code | TFBGA | — |
| Form of Terminal | Ball | — |
| Package Shape | Square | — |
| Operating Temperature Grade | Industrial | — |
| JTAG Interface | TMS, TDI, TDO, TCK (Bank 1) | — |
| Programming Method | JTAG / in-system programmable | — |
| Versorgungsspannung | [DATA_NEEDED: VCCINT and VCCIO levels] | — |
| I/O Standards | Multiple (LVTTL, LVCMOS, SSTL, etc., per MAX V doc; PCI and 1.2 V LVCMOS excluded for JTAG pins) | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | Compliant | Compliant |
| Lead Free | Yes | — |
| Family | — | MAX V (5M240Z) |
| Architecture | — | Non-volatile flash-based |
| Macro Cells | — | 192 |
| Logic Array Blocks (LABs) | — | 4 |
| Maximum Operating Frequency | — | 118.3 MHz |
| Core Supply Voltage | — | 1.8 V (1.71 V to 1.89 V) |
| I/O Banks | — | MultiVolt I/O, 1.5/1.8/2.5/3.3 V compatible |
| Global Clocks | — | 4 |
| User Flash Memory | — | Yes (integrated) |
| Gehäuse | — | 68-ball Micro FBGA (BGA-68) |
| Betriebstemperatur | — | 0 °C to +85 °C (commercial) |
| Programming Interface | — | JTAG (IEEE 1149.1) |