5M570ZE64I5N vs 5M1270ZT144C5N Vergleich
Detaillierter Direktvergleich von 5M570ZE64I5N von Intel und 5M1270ZT144C5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ AktivSpezifikationsvergleich
| Parameter | 5M570ZE64I5N | 5M1270ZT144C5N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,20 | $12,45 |
| Series | MAX V | MAX V |
| Programmable Type | In System Programmable | — |
| Number of Logic Elements / Blocks | 570 | — |
| Number of Macrocells | 440 | — |
| Number of User I/O | 54 | — |
| Propagation Delay tpd(1) Max | 9 ns | — |
| Internal Supply Voltage VCCINT | 1.71 V to 1.89 V (1.8 V typical) | — |
| Betriebstemperaturbereich | -40 C to +100 C (TJ) | — |
| Montageart | Surface Mount | Surface Mount |
| Gehäuse / Bauform | 64-TQFP Exposed Pad (EQFP-64) | — |
| Supplier Device Package | 64-EQFP (7x7 mm) | — |
| Configuration Memory | Non-volatile Flash | Flash (non-volatile, in-system programmable) |
| Programmable I/O Voltage Standards | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) | — |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG in-system programmable (Altera Quartus II) |
| RoHS-Status | Compliant | Compliant |
| Lead-Free | Yes | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements | — | 1270 |
| Macrocells | — | 980 |
| User I/Os | — | 114 |
| Maximum Internal Frequency | — | 118.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 6.2 ns |
| Internal Frequency (typical) | — | 201 MHz |
| User Flash Memory (UFM) | — | 8 Kbits |
| VCCINT (Core Supply) | — | 1.71 V to 1.89 V |
| VCCIO (I/O Supply, per bank) | — | 1.2 V to 3.3 V |
| Number of I/O Banks | — | 4 |
| Supported I/O Standards | — | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins |
| JTAG Interface | — | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) |
| Program/Erase Cycles | — | Up to 100,000 |
| Gehäuse | — | TQFP-144 (22 x 22 mm, 0.5 mm pitch) |
| Betriebstemperatur | — | 0 C to +85 C (commercial grade) |