A54SX72A-2PQG208I vs A54SX72A-2PQ208I Vergleich

Detaillierter Direktvergleich von A54SX72A-2PQG208I von Microchip Technology und A54SX72A-2PQ208I von Microchip Technology. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Microchip Technology
A54SX72A-2PQG208I A54SX72A-2PQG208I - 108K-Gate Antifuse FPGA, 171 I/O | Microchip

A54SX72A-2PQG208I - 108K-Gate Antifuse FPGA, 171 I/O | Microchip

A54SX72A-2PQG208I ✓ Aktiv
Microchip Technology
A54SX72A-2PQ208I A54SX72A-2PQ208I - 108K-Gate Antifuse FPGA, PQFP-208 | Microchip

A54SX72A-2PQ208I - 108K-Gate Antifuse FPGA, PQFP-208 | Microchip

A54SX72A-2PQ208I ✓ Aktiv

Spezifikationsvergleich

Parameter A54SX72A-2PQG208I A54SX72A-2PQ208I
Marke Microchip Technology Microchip Technology
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Aktiv Aktiv
Lagerstatus In Stock In Stock
Stückpreis (USD) $47,90 $89,90
Family SX-A (antifuse FPGA) SX-A (antifuse FPGA)
System Gates 108K 108000 gates
User I/O 171 —
Speed Grade -2 -2
Maximum Toggle/Operating Frequency 217 MHz —
Core Supply Voltage 2.5 V —
I/O Standards TTL, LVTTL, LVCMOS2, 3.3 V PCI, 5 V PCI —
Programming Technology Antifuse (one-time programmable, non-volatile) Antifuse (one-time programmable)
Gehäuse 208-BFQFP (PQFP-208, gull wing) 208-Pin PQFP / BFQFP (28 x 28 mm)
Betriebstemperatur -40C to +85C (Industrial) Industrial (-40C to +85C, I suffix)
Montageart Surface Mount Surface Mount
Terminal Form Gull Wing —
Package Shape Square —
RoHS-Status Lead free (per Kynix listing) —
Moisture Sensitivity Level [DATA_NEEDED: MSL level] —
Number of Logic Cells/Modules [DATA_NEEDED: module count] —
Static Power [DATA_NEEDED: static power] —
Logic Modules / Cells — 4024 cells
Dedicated Flip-Flops — up to 2012
Maximum System Frequency — 294 MHz
User I/O (this package) — 171
Family Maximum User I/O — 360
Versorgungsspannung — 2.5 V (2.25 V to 5.25 V I/O tolerance range per distributor data)
Process Technology — 0.25 um CMOS
Packaging — Tray
Clock Networks — CLKA, CLKB global plus quadrant QCLK networks
Configuration — Non-volatile, active at power-up, no external configuration device

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