ADC12040CIVY vs ADC12020CIVY Vergleich
Detaillierter Direktvergleich von ADC12040CIVY von Texas Instruments und ADC12020CIVY von Texas Instruments. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Texas Instruments
ADC12040CIVY - 12-Bit 40MSPS Pipelined ADC | Texas Instruments
ADC12040CIVY ✓ AktivTexas Instruments
ADC12020CIVY - 12-Bit 20MSPS ADC | Texas Instruments | TQFP-32
ADC12020CIVY ✓ AktivSpezifikationsvergleich
| Parameter | ADC12040CIVY | ADC12020CIVY |
|---|---|---|
| Marke | Texas Instruments | Texas Instruments |
| Kategorie | ADC/DAC | ADC/DAC |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $5,52 | $7,25 |
| Auflösung | 12 bit | 12 bits |
| Abtastrate | 40 MSPS (min 40 MSPS over temperature) | — |
| Number of Channels | 1 input | — |
| Architecture | Pipelined | — |
| Versorgungsspannung | +5V ±5% (single supply) | — |
| Power Consumption | 340 mW (typ) at 40 MHz | — |
| Differential Non-Linearity (DNL) | ±0.4 LSB (typ) | — |
| Signal-to-Noise Ratio (SNR) | 69 dB (typ) at fIN = 10 MHz | — |
| Effective Number of Bits (ENOB) | 11.2 bits (typ) at fIN = 10 MHz | 11.3 bits (typ) at fIN = 10.1 MHz |
| Input Type | Differential (single-ended capable) | Single-ended analog input |
| Reference Type | External, with internal buffer | — |
| Digital Output Interface | Parallel, CMOS, straight binary | — |
| Digital Output Logic Levels | 2.35V to 5V compatible | — |
| Power Down Mode | On-chip (low quiescent between conversions) | Yes |
| Betriebstemperaturbereich | -40C to +85C (industrial) | — |
| Gehäuse | 32-LQFP (NEY) 7x7 mm | 32-LQFP (CIVY) 7x7 mm |
| Montageart | Surface Mount | Surface Mount |
| Pin Family Compatibility | Pin compatible with ADC12010, ADC12020, ADC12L063, ADC12L066 | — |
| RoHS-Status | Compliant (NOPB suffix variants only; check exact suffix) | Compliant (per /NOPB suffix option) |
| Sampling Rate (FS) | — | 20 MSPS (min) |
| Number of Input Channels | — | 1 |
| Conversion Architecture | — | Pipelined with internal sample-and-hold |
| Analog Supply Voltage (AVDD) | — | +5 V (single) / +5 V analog with ±5 V option |
| Digital Supply Voltage (DVDD) | — | 2.35 V to 5 V |
| Differential Nonlinearity (DNL) | — | ±0.35 LSB (typ) |
| Power Consumption (20 MHz) | — | 185 mW (typ) |
| Reference Buffer | — | On-chip |
| Digital I/O Compatibility | — | TTL/CMOS, 2.35 V to 5 V |
| Betriebstemperatur | — | -40C to +85C |
| MSL-Level | — | [DATA_NEEDED: MSL level] |