ADC1213D080HN-C18 vs ADC1112D125HN-C18 Vergleich
Detaillierter Direktvergleich von ADC1213D080HN-C18 von Renesas Electronics und ADC1112D125HN-C18 von Renesas Electronics. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Renesas Electronics
ADC1213D080HN-C18 - 12-bit 80MSPS Dual ADC with JESD204A | Renesas
ADC1213D080HN-C18 ✓ AktivRenesas Electronics
ADC1112D125HN-C18 - Dual 11-bit 125MSPS ADC, LVDS/CMOS | Renesas
ADC1112D125HN-C18 ✓ AktivSpezifikationsvergleich
| Parameter | ADC1213D080HN-C18 | ADC1112D125HN-C18 |
|---|---|---|
| Marke | Renesas Electronics | Renesas Electronics |
| Kategorie | ADC/DAC | ADC/DAC |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,75 | $9,48 |
| Auflösung | 12 bit | 11-bit |
| Number of Channels | 2 (dual, simultaneous sampling) | 2 (dual, simultaneous sampling) |
| Sampling Rate per Channel | 80 MSPS | — |
| Architecture | Pipelined | — |
| Data Output Interface | JESD204A (serial, up to 3.125 Gbps lane) | — |
| Gehäuse | 56-VFQFPN exposed pad (8x8 mm) | HVQFN-64 (8x8 mm with exposed thermal pad) |
| Analog Supply Voltage (AVDD) | 1.8 V | 3.0 V to 3.6 V |
| Digital/Drive Supply Voltage (DRVDD) | 3.3 V | — |
| Input Type | Differential / single-ended (configurable) | Single-ended analog inputs (per channel) |
| Input Bandwidth | [DATA_NEEDED: full-power input bandwidth MHz] | — |
| SNR | [DATA_NEEDED: SNR dBFS at fIN] | — |
| ENOB | [DATA_NEEDED: ENOB bits at fIN] | — |
| SFDR | [DATA_NEEDED: SFDR dBc] | — |
| Power Consumption | [DATA_NEEDED: power mW per channel at 80 MSPS] | — |
| Betriebstemperaturbereich | -40 C to +85 C (industrial) | -40 C to +85 C |
| Configuration Interface | SPI-compatible serial | — |
| Montageart | Surface Mount | Surface Mount |
| MSL-Level | 3 (per JEDEC J-STD-020) | 3 (168 hours) |
| RoHS-Status | Compliant | Compliant |
| Lead-Free | Yes | — |
| Sample Rate (Max) | — | 125 Msps |
| Digital I/O Supply (OVDD) | — | 1.8 V to 3.3 V |
| Output Interface | — | CMOS or LVDS DDR (selectable) |
| Reference | — | Internal programmable (0-6 dB in 1 dB steps) or external |
| Control Interface | — | SPI (3-wire, mode configuration) |
| Power-Down Mode | — | Yes, per-channel via SPI |