ADC32J44IRGZ25 vs ADS62P48IRGC25 Vergleich
Detaillierter Direktvergleich von ADC32J44IRGZ25 von Texas Instruments und ADS62P48IRGC25 von Texas Instruments. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Texas Instruments
ADS62P48IRGC25 - Dual 14-Bit 210MSPS ADC | Texas Instruments
ADS62P48IRGC25 ✓ AktivSpezifikationsvergleich
| Parameter | ADC32J44IRGZ25 | ADS62P48IRGC25 |
|---|---|---|
| Marke | Texas Instruments | Texas Instruments |
| Kategorie | ADC/DAC | ADC/DAC |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $42,10 | $49,20 |
| Manufacturer | Texas Instruments | — |
| Series | ADC32J4x | — |
| Number of Channels | 2 | 2 (Dual) |
| Auflösung | 14 bit | 14 bit |
| Sampling Rate (max) | 125 MSPS | — |
| Architecture | Pipelined | Pipelined |
| Input Type | Differential | Differential analog inputs |
| Data Interface | JESD204B | — |
| Number of Lanes | Up to 2 | — |
| Max Lane Rate | 3.125 Gbps | — |
| Supply Voltage (Analog) | 1.8 V | — |
| Supply Voltage (Digital) | 1.8 V | — |
| Power Consumption | 227 mW/Ch at 160 MSPS | — |
| SNR | 72.2 dBFS at fIN = 70 MHz | — |
| SFDR | 87 dBc at fIN = 70 MHz | — |
| Channel Isolation | 105 dB | — |
| Betriebstemperatur | -40C to +85C (Industrial) | — |
| Gehäuse | 48-VQFN (7x7 mm) | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | Compliant | Compliant |
| Sample Rate (max) | — | 210 MSPS |
| Output Interface | — | DDR LVDS / Parallel CMOS (selectable) |
| Analog Supply Voltage | — | 1.8 V |
| Digital Supply Voltage | — | 3.3 V |
| Betriebstemperaturbereich | — | -40 C to +85 C (Industrial) |
| Gehäuse / Bauform | — | 64-VQFN (RGC) 9x9 mm (HVQCCN) |
| Pin-Anzahl | — | 64 |
| MSL-Level | — | 3 |
| Lead Free | — | Yes |
| Input Clock Type | — | LVDS differential clock |
| Internal Dither | — | Yes (programmable) |
| Programmable Gain | — | Yes (improves SFDR at lower FS inputs) |