ATF16V8B-15PC vs ATF16V8B-15JC Vergleich
Detaillierter Direktvergleich von ATF16V8B-15PC von Microchip Technology und ATF16V8B-15JC von Microchip Technology. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Microchip Technology
ATF16V8B-15PC - 15 ns 250-Gate EEPLD | Microchip Technology
ATF16V8B-15PC ✓ AktivMicrochip Technology
ATF16V8B-15JC - 15ns 8-Macrocell EEPLD | Microchip Technology
ATF16V8B-15JC ✓ AktivSpezifikationsvergleich
| Parameter | ATF16V8B-15PC | ATF16V8B-15JC |
|---|---|---|
| Marke | Microchip Technology | Microchip Technology |
| Kategorie | Logic ICs | Logic ICs |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Device Type | Electrically erasable programmable logic device (EEPLD) | Electrically erasable programmable logic device (EEPLD) |
| Programmable Gate Capacity | 250 gates | — |
| Maximum Inputs | Up to 16 inputs | — |
| I/O Count | 8 I/Os | Up to 8 I/Os |
| Macrocell Count | 8 macrocells | 8 macrocells |
| Speed Grade | 15 ns | — |
| Family Maximum Pin-to-Pin Delay | 7.5 ns | — |
| Versorgungsspannung | 5 V | 5 V |
| Configuration Technology | Electrically erasable Flash memory | — |
| Logic Architecture | 16V8 architecture with 8 outputs | — |
| Output Product-Term Allocation | 8 product terms per output | — |
| Operating Mode Support | Three software-selected modes of operation | — |
| Power Class | Standard power | — |
| Gehäuse | 20-pin PDIP | 20-pin PLCC (9x9 mm) |
| Package Pitch | 7.62 mm (0.300 inch) | — |
| Package Finish | Green package | — |
| Montageart | Through-hole | Surface mount |
| Family Standby Current | 5 mA | — |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS compliance status] |
| REACH Status | unknown | [DATA_NEEDED: REACH compliance status] |
| AEC-Q100 Qualification | not_applicable | — |
| Betriebstemperaturbereich | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Architecture | — | 16V8 SPLD architecture with 8 macrocells |
| Propagation Delay | — | 15 ns |
| Logic Capacity | — | 250 gates |
| Maximum Input Count | — | Up to 16 inputs |
| Configuration Memory | — | Electrically erasable Flash memory |
| Product Terms per Output | — | 8 product terms per output |
| Architecture Compatibility | — | Emulates many 20-pin PALs |
| Versorgungsstrom | — | [DATA_NEEDED: operating and standby supply current] |