EP1810GC-35AB vs EP1810GM883 Vergleich

Detaillierter Direktvergleich von EP1810GC-35AB von Altera und EP1810GM883 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1810GC-35AB EP1810GM883
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,95 $175,00
Product Family Classic EPLD —
Technology CMOS EPROM —
Number of Macrocells 48 —
Number of Usable Gates 1200 —
Maximum Inputs 64 —
Maximum Outputs 48 —
Number of I/O Pins 48 —
Dedicated Input Pins 12 —
Propagation Delay (tPD) 35 ns —
Maximum Toggle Frequency 62.5 MHz —
Supply Voltage (VCC) 5 V —
Package Type Pin Grid Array (PGA), ceramic —
Betriebstemperatur [DATA_NEEDED: operating temperature range] -55C to +125C (MIL-STD-883 Class B)
Programming Method UV-erasable EPROM, in-system via JTAG-like interface —
RoHS-Status unknown [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data]
Family — Classic EPLD (EP1810 series)
Device Type — UV-Erasable Programmable Logic Device (EPLD)
Macrocells — 48
Dedicated Inputs — 12
User I/O Pins — 48
Total Terminals — 68
Global Clocks — 4
Supply Voltage (Vcc) — 4.5 V to 5.5 V (nominal 5 V)
Propagation Delay (tpd) — 45 ns (max)
Maximum Toggle Frequency (fmax) — [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade]
Process Technology — CMOS, UV-erasable
Gehäuse — 68-Pin Ceramic Pin Grid Array (PGA)
Screening — MIL-STD-883 Class B (suffix '883' denotes MIL processing)
Montageart — Through-Hole (PGA socket)
Lead-Free — [DATA_NEEDED: military 883B screened parts commonly use SnPb finish]

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