EP1810GI-45 vs EP1810GC-35 Vergleich
Detaillierter Direktvergleich von EP1810GI-45 von Altera und EP1810GC-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester
EP1810GC-35 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP1810GI-45 | EP1810GC-35 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $56,40 | $177,12 |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 16 |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Speed Grade | -45 | — |
| Technology | CMOS | CMOS, UV-erasable EPROM cells |
| Package Type | Ceramic Pin Grid Array with UV window | — |
| Pin-Anzahl | 68 | — |
| Montageart | Through-Hole | Through Hole |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| RoHS-Status | Non-compliant (ceramic PGA) | Not applicable (legacy ceramic package) |
| Lead-Free | No | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Versorgungsspannung | [DATA_NEEDED: VCC range] | [DATA_NEEDED: VCC range] |
| Logic Family | — | Altera Classic EPLD |
| Gehäuse | — | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| Anzahl der Pins | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | UV erasure + EPROM programming |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |