EP1810JC-25 vs EP1810GC-35AB Vergleich
Detaillierter Direktvergleich von EP1810JC-25 von Intel und EP1810GC-35AB von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1810JC-25 | EP1810GC-35AB |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $6,80 | $9,95 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera/Intel Classic EPLD (EP1810 series) | — |
| Macrocells | 48 | — |
| Propagation Delay (tPD) | 25 ns | 35 ns |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | 62.5 MHz |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Betriebstemperatur | -40 °C to 85 °C (industrial, per distributor listings) | [DATA_NEEDED: operating temperature range] |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | CMOS EPROM |
| Gehäuse | 28-pin ceramic DIP (J) with quartz window | — |
| Montageart | Through-hole | — |
| Erasure Method | UV light (windowed package) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | unknown |
| Lebenszyklusstatus | NRND (Not Recommended for New Designs) | — |
| Product Family | — | Classic EPLD |
| Number of Macrocells | — | 48 |
| Number of Usable Gates | — | 1200 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Number of I/O Pins | — | 48 |
| Dedicated Input Pins | — | 12 |
| Package Type | — | Pin Grid Array (PGA), ceramic |
| Programming Method | — | UV-erasable EPROM, in-system via JTAG-like interface |