EP1810JC35 vs EP1810GC-35AB Vergleich
Detaillierter Direktvergleich von EP1810JC35 von Altera und EP1810GC-35AB von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1810JC35 | EP1810GC-35AB |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $9,95 |
| Family | Altera Classic EPLD | — |
| Product Type | UV-erasable / OTP Complex PLD (EPLD) | — |
| Macrocells | 48 | — |
| Logic Gates (typ.) | [DATA_NEEDED: logic gates count] | — |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count for PLCC-68] | — |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximale Taktfrequenz | 40 MHz | — |
| Supply Voltage (VCC max) | 5.25 V | — |
| Supply Voltage (VCC min) | [DATA_NEEDED: VCC minimum] | — |
| Process Technology | CMOS EPROM cell | — |
| Betriebstemperatur | 0 C to +70 C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Gehäuse | PLCC-68 (J-lead, ceramic) | — |
| Package Code | QCCJ | — |
| Terminal Form | J-BEND | — |
| Number of Terminals | 68 | — |
| Programming | UV-erase (windowed) or OTP | — |
| Development Tool | Altera MAX+plus II / A+plus | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance for EP1810JC35] | unknown |
| Product Family | — | Classic EPLD |
| Technology | — | CMOS EPROM |
| Number of Macrocells | — | 48 |
| Number of Usable Gates | — | 1200 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Number of I/O Pins | — | 48 |
| Dedicated Input Pins | — | 12 |
| Maximum Toggle Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Package Type | — | Pin Grid Array (PGA), ceramic |
| Programming Method | — | UV-erasable EPROM, in-system via JTAG-like interface |