EP1810JI-45 vs EP1810JM-45 Vergleich

Detaillierter Direktvergleich von EP1810JI-45 von Altera und EP1810JM-45 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1810JI-45 EP1810JM-45
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,75 $14,20
Manufacturer Altera (now Intel FPGA) —
Series Classic EPLD Family —
Device Type UV-Erasable / OTP Complex PLD —
Macrocell Count 48 —
Maximum Operating Frequency 33.3 MHz —
Propagation Delay (tPD) 50 ns —
Configurable I/O Lines 48 —
Dedicated Inputs 12 —
Technology CMOS EPROM CMOS, UV-EPROM configuration
Package Code QCCJ JM (windowed ceramic, UV-erasable)
Package Type 68-pin JLCC (J-leaded ceramic chip carrier) JLCC-68 (ceramic J-leaded chip carrier)
Terminal Form J BEND —
Package Shape SQUARE —
Number of Terminals 68 —
Temperature Grade INDUSTRIAL —
Betriebstemperatur -40 °C to +85 °C -55 C to +125 C (military grade)
Versorgungsspannung 5 V (TTL compatible) —
Programming Method UV-erase (windowed) / OTP via JEDEC —
Device Family — Classic EPLD (EP1810 series)
Macrocells — 48
Usable Gates — ~900 gates
Propagation Delay (tpd) — 45 ns (max, -45 speed grade)
Supply Voltage (VCC) — 4.5 V to 5.5 V
Pin-Anzahl — 68
I/O Compatibility — CMOS / TTL
Configuration Method — JEDEC fuse map, EPROM programmer
Programming Technology — UV-erasable EPROM (non-volatile, instant-on)
Montageart — Surface Mount (J-lead)
Logic Type — EPLD / PLD (programmable logic device)
RoHS-Status — [DATA_NEEDED: RoHS status - legacy mil-spec part]
MSL-Level — [DATA_NEEDED: MSL level]

Datenblätter & Ressourcen

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