EP1810LC-25T vs EP1810LC-20T Vergleich
Detaillierter Direktvergleich von EP1810LC-25T von Intel und EP1810LC-20T von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1810LC-25T | EP1810LC-20T |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,40 | $9,95 |
| Family | Altera Classic EP1810 | Altera Classic EPLD |
| Device Type | EPLD (Erasable/OTP Complex PLD) | — |
| Macrocells | 48 (4 quadrants x 12 macrocells) | 48 |
| Usable Gates | Approx. 900 | 900 gates |
| Dedicated Inputs | 16 | — |
| Bidirectional I/O Pins | 48 | — |
| External Clocks | 4 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 5 V nominal | 5 V |
| Betriebstemperatur | 0 °C to +70 °C (commercial) | 0C to +70C (commercial) |
| Gehäuse | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) | — |
| Montageart | Surface Mount | Surface Mount (socket-compatible) |
| Technology | CMOS, UV-erasable / OTP | — |
| I/O Standard | TTL-compatible 5 V | — |
| RoHS-Status | [DATA_NEEDED: RoHS status - confirm with manufacturer] | Non-compliant (legacy 5V PLCC) |
| Programming Tool | Altera MAX+PLUS II / Quartus Classic | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 4 x 12 macrocells |
| Maximum Toggle Frequency | — | 50 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 20 ns |
| Package Type | — | PLCC-68 (J-lead) |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |
| Programming Interface | — | JTAG (IEEE 1149.1) and Altera Master/Slave serial |
| Shipping Format | — | Tape & Reel ("T" suffix) |