EP1810LI-45 vs EP1810LC-45 Vergleich
Detaillierter Direktvergleich von EP1810LI-45 von Rochester Electronics und EP1810LC-45 von Rochester Electronics. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Rochester Electronics
EP1810LI-45 - Classic EPLD, 900 Gates, 48 Macrocells, 45ns, PQCC68 | Rochester Electronics (Altera)
EP1810LI-45 ✓ AktivRochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 ObsoleteSpezifikationsvergleich
| Parameter | EP1810LI-45 | EP1810LC-45 |
|---|---|---|
| Marke | Rochester Electronics | Rochester Electronics |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $64,10 | $49,90 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic | Altera Classic EPLD |
| Usable Gates | 900 | 900 |
| Macrocells | 48 | — |
| Maximum User I/O | 64 inputs / 48 outputs | — |
| Pin-to-Pin Logic Delay (tPD) | 45 ns | — |
| Counter Frequency (fCNT) | up to 100 MHz | — |
| Setup Time (tSU) | [DATA_NEEDED: setup time] | — |
| Technology | CMOS, UV-erasable EPROM configuration | — |
| Versorgungsspannung | 5 V | — |
| Betriebstemperaturbereich | -40 C to +85 C (Industrial, 'I' suffix) | — |
| Gehäuse | 68-pin PLCC / PQCC68 (J-Lead) | 68-pin PLCC (J-lead) |
| Logic Blocks | 12 LABs of 4 macrocells each | — |
| Configuration Memory | Non-volatile UV-erasable EPROM | — |
| Programming Method | Altera programming hardware with MAX+PLUS II / legacy tools | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status of Rochester-sourced part] |
| Manufacturer | Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Macro Cells | — | 48 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Logic Array Blocks | — | 4 |
| Propagation Delay (tpd) | — | 45 ns |
| Maximum Operating Frequency | — | 22.2 MHz |
| Supply Voltage (Vcc) | — | 5 V (±5%) |
| Process Technology | — | 5 V CMOS EPROM |
| Betriebstemperatur | — | 0 °C to +70 °C (commercial) |
| Montageart | — | Surface Mount (PLCC socket compatible) |
| Lead-Free | — | [DATA_NEEDED: lead-free finish] |