EP1K10TC100-3 vs EP1K10TC100-2N Vergleich
Detaillierter Direktvergleich von EP1K10TC100-3 von Intel und EP1K10TC100-2N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP1K10TC100-2N - ACEX-1K FPGA, 10K Gates, 576 Cells | Altera
EP1K10TC100-2N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP1K10TC100-3 | EP1K10TC100-2N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $8,25 |
| Family | ACEX-1K | ACEX-1K |
| Number of Logic Elements (LEs) | 576 | — |
| Typical Gates | 10,000 | 10,000 |
| Number of LABs | 72 | — |
| Number of EABs | 3 | — |
| Total RAM Bits | 12,288 | — |
| User I/O Pins | 66 | — |
| Operating Frequency (max) | 200 MHz | — |
| Speed Grade | -3 (fastest commercial) | -2 |
| Core Voltage | 2.5 V | — |
| Process Technology | 0.22 µm CMOS | 0.22 um CMOS |
| Gehäuse | 100-pin TQFP (TQFP-100) | 100-pin TQFP (1.0 mm body, 0.5 mm pitch) |
| Betriebstemperatur | [DATA_NEEDED: operating temperature grade] | 0 C to +70 C (commercial) |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Lead-free / RoHS compliant |
| Programming Interface | JTAG (IEEE 1149.1) | — |
| Supported I/O Standards | LVTTL, LVCMOS, PCI | — |
| Memory Configuration | Dual-port RAM supported (per family) | — |
| Logic Elements / Cells | — | 576 |
| Logic Array Blocks (LABs) | — | 72 |
| Embedded Memory (EAB) | — | 12,288 bits |
| Maximum User I/O | — | 66 |
| Core Voltage (VCCINT) | — | 2.5 V |
| I/O Voltage (VCCIO) | — | 1.8 V / 2.5 V / 3.3 V / 5 V |
| Maximum Frequency | — | 200 MHz |
| Configuration Modes | — | Passive Serial, Active Serial, JTAG |