EP1K30QC208-3 vs EP1K100QC208-3 Vergleich
Detaillierter Direktvergleich von EP1K30QC208-3 von Intel und EP1K100QC208-3 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP1K30QC208-3 - ACEX-1K FPGA, 30K Gates, 208-PQFP | Intel
EP1K30QC208-3 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP1K30QC208-3 | EP1K100QC208-3 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $60,04 |
| Family | ACEX-1K | — |
| Logic Elements | 1,728 | — |
| Typical Gates | 30,000 | — |
| Maximum System Gates | 119,000 | — |
| Embedded Array Blocks (EABs) | 6 | — |
| Total RAM Bits | 24,576 | 49,152 bits |
| Maximum User I/O | 147 | 147 |
| Core Voltage | 2.5 V | — |
| Speed Grade | -3 | -3 |
| Gehäuse | 208-pin PQFP (Plastic Quad Flat Pack) | — |
| Betriebstemperatur | 0C to +70C (commercial) | — |
| Montageart | Surface Mount | Surface Mount |
| Process Technology | SRAM-based LUT, 0.18 um | 0.22 um CMOS |
| I/O Standards Supported | LVTTL, LVCMOS, PCI | [DATA_NEEDED: supported I/O standards] |
| Programming Interface | IEEE 1149.1 JTAG, ByteBlaster | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Product Family | — | ACEX 1K |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Typical Gate Count | — | 100,000 gates |
| Number of Logic Elements | — | 4,992 |
| Logic Array Blocks (LABs) | — | 624 |
| Maximum Internal Clock Frequency | — | 200 MHz |
| Core Supply Voltage | — | 2.5 V |
| Package Type | — | 208-Pin BFQFP (PQFP) |
| Number of Terminals | — | 208 |
| Terminal Form | — | Gull Wing |
| Package Shape | — | Square |
| Temperature Grade | — | Commercial |
| RoHS / Lead-Free Suffix | — | No -N suffix; compliance not verified in retrieved source data |
| Configuration Memory | — | SRAM-based loadable PLD |