EP1K30TC144-1N vs EP1K30TC144-3 Vergleich
Detaillierter Direktvergleich von EP1K30TC144-1N von Altera und EP1K30TC144-3 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1K30TC144-1N | EP1K30TC144-3 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $11,50 | $10,80 |
| Series | ACEX-1K | ACEX-1K |
| Number of Logic Elements (LEs) | 1,728 | — |
| Typical Gates | 30,000 | 30,000 |
| Number of Logic Array Blocks (LABs) | 216 | — |
| Embedded Memory (EAB) | 24,576 bits (6 EABs) | — |
| Number of User I/O | 102 | 102 |
| Number of I/O Banks | 4 | — |
| Package Type | 144-LQFP (TQFP) | — |
| Montageart | Surface Mount | Surface Mount |
| Core Voltage | 2.5 V | — |
| I/O Voltage | 3.3 V (LVCMOS/LVTTL); 2.5 V tolerant | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | — |
| Process Technology | 0.18 µm SRAM | 0.22 µm SRAM |
| Configuration | SRAM-based, JTAG (IEEE 1149.1) + serial/parallel passive | — |
| PLLs | 6 (per device family) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status from datasheet] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL-Level | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Logic Elements / Cells | — | 1,728 |
| Total RAM Bits | — | 24,576 |
| Number of LABs/CLBs | — | 216 |
| Maximum System Gates | — | 56,000 |
| Number of Logic Array Blocks | — | 216 |
| Supply Voltage (Core) | — | 2.5 V |
| I/O Voltage Standard | — | 2.5 V LVCMOS / LVTTL (MultiVolt up to 5.0 V tolerant) |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Gehäuse | — | 144-LQFP / 144-TQFP (22x22 mm, 0.5 mm pitch) |
| Speed Grade | — | -3 (slowest speed bin) |
| Configuration Method | — | Serial configuration device (EPC2/EPC8 compatible) |
| Boundary Scan | — | IEEE 1149.1 JTAG compliant |
| Number of Global Clocks | — | 8 |