EP1K50FC256-1N vs EP1K50FC256-2 Vergleich

Detaillierter Direktvergleich von EP1K50FC256-1N von Intel und EP1K50FC256-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1K50FC256-1N EP1K50FC256-2
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $15,10 $62,00
Family ACEX-1K ACEX 1K Family
Series ACEX-1K (2.5 V) ACEX-1K
Maximum Logic Elements 2,880 —
Logic Array Blocks (LABs) 360 —
Typical Gates 50,000 50,000
Maximum System Gates 199,000 —
Embedded Memory (EAB) Bits 40,960 bits —
User I/O Pins 186 —
Core Supply Voltage 2.5 V (2.375 V to 2.625 V) —
Maximum Internal Frequency 250 MHz —
Process Technology 0.22 um CMOS 0.22 µm CMOS
Typical Operating Current 5 mA —
Speed Grade -1 (commercial) —
Betriebstemperatur 0 C to 70 C (commercial) 0°C to +70°C (commercial)
Gehäuse 256-ball FBGA (FineLine BGA) —
Montageart Surface Mount Surface Mount
Lead Status Lead-free (-N suffix) —
RoHS-Status Compliant Compliant
Programmable I/O Standards LVTTL, LVCMOS, PCI, GTL+ —
Configuration Method SRAM-based, JTAG (IEEE 1149.1) SRAM-based, volatile configuration
Logic Cells / Elements — 2,880
Number of LABs/CLBs — 360
User I/Os — 186
Total RAM Bits — 40,960
Number of Gates — 50,000
Voltage - Supply — 2.375 V to 2.625 V (nominal 2.5 V)
Propagation Delay — 0.4 ns (per Partstack listing)
Gehäuse / Bauform — 256-BGA (FineLine BGA, 17x17 mm)
Montagestil — SMD/SMT
Programming Type — In-System Programmable via JTAG (IEEE 1149.1)
REACH Status — Compliant
MSL-Level — [DATA_NEEDED: MSL level]

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