EP1K50FC256-2 vs EP1K50F256-2N Vergleich
Detaillierter Direktvergleich von EP1K50FC256-2 von Altera und EP1K50F256-2N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1K50FC256-2 | EP1K50F256-2N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $62,00 | $21,80 |
| Series | ACEX-1K | — |
| Family | ACEX 1K Family | ACEX 1K |
| Logic Cells / Elements | 2,880 | — |
| Typical Gates | 50,000 | 50,000 |
| Number of LABs/CLBs | 360 | — |
| User I/Os | 186 | — |
| Total RAM Bits | 40,960 | 40,960 |
| Number of Gates | 50,000 | — |
| Voltage - Supply | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm SRAM |
| Propagation Delay | 0.4 ns (per Partstack listing) | — |
| Betriebstemperatur | 0°C to +70°C (commercial) | 0C to +70C (commercial) |
| Gehäuse / Bauform | 256-BGA (FineLine BGA, 17x17 mm) | — |
| Montageart | Surface Mount | — |
| Montagestil | SMD/SMT | — |
| Programming Type | In-System Programmable via JTAG (IEEE 1149.1) | — |
| Configuration Method | SRAM-based, volatile configuration | SRAM, serial or parallel via Altera EPC devices |
| RoHS-Status | Compliant | [DATA_NEEDED: RoHS status] |
| REACH Status | Compliant | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Logic Elements | — | 2,880 |
| Logic Array Blocks (LABs) | — | 360 |
| Embedded Array Blocks (EABs) | — | 5 |
| Maximum User I/O | — | 186 |
| Gehäuse | — | 256-ball FineLine BGA (F256), 1.0 mm pitch |
| Speed Grade | — | -2 |
| Core Voltage | — | 3.3 V |
| I/O Standards | — | LVTTL, LVCMOS, 3.3 V / 2.5 V / 1.8 V / 1.5 V |
| Programming Interface | — | JTAG (IEEE 1149.1) / in-system programmable |