EP1K50QC208-1N vs EP1K50QC208-3N Vergleich

Detaillierter Direktvergleich von EP1K50QC208-1N von Altera und EP1K50QC208-3N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1K50QC208-1N EP1K50QC208-3N
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Aktiv Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $0,00 $13,85
Product Type Field Programmable Gate Array (FPGA) —
Family ACEX 1K ACEX-1K
Number of Logic Elements 2880 LE —
Number of LABs 360 LABs —
Embedded Memory Bits 40960 bits (40 kbit) —
Embedded RAM Capability RAM, ROM, dual-port RAM, FIFO (per ACEX 1K architecture) —
Maximum User I/O 147 I/O —
Typical Gate Count 50000 gates —
Core Supply Voltage 2.5 V —
Maximum Operating Frequency 250 MHz 166.67 MHz
Speed Grade -1 —
Process Technology 0.22 um CMOS 0.22 µm CMOS
Package Type 208-BFQFP (PQFP-208) —
Terminal Form Gull wing —
Package Shape Square —
Montageart Surface Mount Surface Mount
Lead-Free Finish N suffix, lead-free finish per Altera part numbering —
Betriebstemperaturbereich [DATA_NEEDED: exact operating temperature range] —
Typical Gates — 50,000
Logic Elements (LEs) — 2,880
Logic Array Blocks (LABs) — 360
Embedded RAM — 40,960 bits (10 EABs × 4,096 bits)
Maximum User I/Os — 147
Pin-to-Pin Logic Delay — 0.5 ns (typical, -3 speed grade)
Core Supply Voltage (VCCINT) — 2.5 V
I/O Supply Voltage (VCCIO) — 3.3 V (PCI-compatible I/O banks)
Gehäuse — 208-pin PQFP / BFQFP (Plastic Quad Flat Pack)
Betriebstemperatur — 0 °C to +70 °C (Commercial)
Programming Interface — IEEE 1149.1 JTAG + in-system configurable
Lead-Free / RoHS — Compliant (Pb-free terminal finish per 'N' suffix)

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