EP1K50QC208-3 vs EP1K50QC208-2N Vergleich
Detaillierter Direktvergleich von EP1K50QC208-3 von Altera und EP1K50QC208-2N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1K50QC208-3 | EP1K50QC208-2N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $12,10 | $27,80 |
| Family | ACEX 1K | ACEX 1K |
| Logic Elements / Cells | 2,880 | — |
| Typical Gates | 50,000 | 50,000 |
| RAM Bits | 40,960 | — |
| Logic Array Blocks (LABs) | 360 | 360 |
| Embedded Array Blocks (EABs) | 12 | — |
| User I/O Pins | 147 | — |
| Maximum Operating Frequency | 166.67 MHz | — |
| Speed Grade | -3 | — |
| Core Supply Voltage | 2.5 V | 2.5 V |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Gehäuse | 208-pin PQFP (BFQFP) | 208-pin PQFP (BFQFP) |
| Montageart | Surface Mount | Surface Mount (Gull-Wing) |
| Betriebstemperatur | Commercial (0°C to +70°C) [DATA_NEEDED: exact range] | 0 °C to 85 °C (Commercial) |
| Configuration Mode | Passive Serial, Active Serial, JTAG | — |
| I/O Standards | LVTTL, LVCMOS, PCI | — |
| Design Tool Support | Quartus II, MAX+PLUS II | — |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS status] |
| Series | — | ACEX-1K |
| Logic Elements | — | 2,880 |
| Embedded Memory (EAB SRAM) | — | 40 kbit |
| User I/Os | — | 147 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Maximum Toggle Frequency | — | 200 MHz |
| Pin-to-Pin Delay (LE) | — | 0.4 ns (per data sheet snippet) |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O supply voltage] |
| Configuration Interface | — | JTAG (IEEE 1149.1), Serial (PS/AS) |
| MSL-Level | — | [DATA_NEEDED: MSL level] |