EP1K50TI144-1X vs EP1K50TI144-2X Vergleich

Detaillierter Direktvergleich von EP1K50TI144-1X von Intel und EP1K50TI144-2X von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Intel
EP1K50TI144-2X EP1K50TI144-2X - 50K-Gate ACEX 1K FPGA | Intel | 144-TQFP

EP1K50TI144-2X - 50K-Gate ACEX 1K FPGA | Intel | 144-TQFP

EP1K50TI144-2X ⚠ Letzte Bestellmöglichkeit

Spezifikationsvergleich

Parameter EP1K50TI144-1X EP1K50TI144-2X
Marke Intel Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Letzte Kaufgelegenheit
Lagerstatus In Stock In Stock
Stückpreis (USD) $10,95 $17,20
Family ACEX 1K ACEX 1K
Series EP1K50 —
Device Type FPGA (Field Programmable Gate Array) —
Equivalent Gates 50,000 —
Logic Elements / Cells 2,880 —
Configurable Logic Blocks (CLBs) 360 —
Maximum User I/O Pins 102 102
Dedicated Input Pins 6 —
Number of Terminals 144 —
Package Code QFP / TQFP-144 (Industrial) —
Package Style Low-profile Fine-pitch Quad Flat Pack (LFQFP / LQFP), 0.5 mm pitch —
Terminal Form Gull Wing —
Supply Voltage (VCCINT) 2.375 V to 2.625 V (nominal 2.5 V) —
Maximale Taktfrequenz 90 MHz —
Betriebstemperatur -40 C to +85 C (Industrial) —
Configuration Method Volatile SRAM, external configuration device required —
Montageart Surface Mount Surface Mount
RoHS-Status [DATA_NEEDED: RoHS status] unknown
Speed Grade -1 (slowest, lowest cost) -2 (mid-tier)
Design Toolchain Quartus II (legacy support) —
Logic Elements — 2,880
Typical Gate Count — 50,000 gates
Configurable Logic Blocks (LABs/CLBs) — 360
Embedded SRAM (bits) — 40,960
Embedded Array Blocks (EABs) — 5 (per datasheet family)
Gehäuse — 144-pin TQFP (TQFP-144), 0.5 mm pitch, gull-wing
Temperature Grade — Industrial (-40 °C to +100 °C)
Core Supply Voltage (VCCINT) — 2.5 V
I/O Supply Voltage (VCCIO) — 3.3 V / 2.5 V / 1.8 V (per bank)
Process Technology — 0.18 µm CMOS, SRAM-based
Maximum Internal Frequency — up to 833 MHz (per family)
Configuration Mode — JTAG (IEEE 1149.1), passive serial, passive parallel asynchronous
Supported I/O Standards — LVTTL, LVCMOS, PCI

Datenblätter & Ressourcen

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