EP1K50TI144-2N vs EP1K50TI144-3N Vergleich

Detaillierter Direktvergleich von EP1K50TI144-2N von Altera und EP1K50TI144-3N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1K50TI144-2N EP1K50TI144-3N
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,95 $19,80
Family ACEX-1K ACEX 1K (EP1K)
Logic Elements 40,960 2,880
Typical Gates 50,000 50,000
Logic Cells 2,880 —
Logic Array Blocks (LABs) 360 —
User I/O Count 102 —
Maximum Operating Frequency 166.67 MHz —
Process Technology 0.22 µm 0.22 µm CMOS, SRAM-based
Embedded RAM Bits 40,960 (12 ESBs) —
Gehäuse 144-LQFP (TQFP, 0.5 mm pitch) 144-pin TQFP (Industrial, Pb-free)
Operating Voltage (VCCINT) 2.5 V —
Montageart Surface Mount Surface Mount
Betriebstemperatur -40C to +85C (industrial, "N" suffix) -40 °C to +85 °C (Industrial)
Speed Grade -2 (faster) -3 (fastest ACEX 1K grade)
Configuration Method SRAM / JTAG (IEEE 1149.1) —
Lead-Free / RoHS Check supplier (ACEX-1K predates RoHS mandate) —
Series — EP1K50
Embedded Array Blocks (EABs) — 40 (4 Kbit each)
Embedded Memory (EAB SRAM) — 40,960 bits
Maximum User I/O — 102
Dedicated Inputs — 6
Core Voltage (VCCINT) — 2.375 V to 2.625 V (nominal 2.5 V)
I/O Bank Voltage (VCCIO) — 2.375 V to 5.0 V (multiVolt I/O)
Maximum Internal Frequency — 166.67 MHz (process node data)
Configuration Interface — JTAG (IEEE 1149.1) + passive-serial
RoHS-Status — Compliant (Pb-free terminal finish, "N" suffix)
MSL-Level — [DATA_NEEDED: MSL level]
Supply Current (typ/ICC) — [DATA_NEEDED: ICC standby]

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