EP1K50TI144-2X vs EP1K50TI144-2 Vergleich
Detaillierter Direktvergleich von EP1K50TI144-2X von Intel und EP1K50TI144-2 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP1K50TI144-2X - 50K-Gate ACEX 1K FPGA | Intel | 144-TQFP
EP1K50TI144-2X ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EP1K50TI144-2X | EP1K50TI144-2 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,20 | $27,85 |
| Family | ACEX 1K | ACEX-1K |
| Logic Elements | 2,880 | — |
| Typical Gate Count | 50,000 gates | — |
| Configurable Logic Blocks (LABs/CLBs) | 360 | — |
| Embedded SRAM (bits) | 40,960 | — |
| Embedded Array Blocks (EABs) | 5 (per datasheet family) | [DATA_NEEDED: EAB count] |
| Maximum User I/O Pins | 102 | — |
| Gehäuse | 144-pin TQFP (TQFP-144), 0.5 mm pitch, gull-wing | 144-LQFP (TQFP-144) |
| Speed Grade | -2 (mid-tier) | -2 |
| Temperature Grade | Industrial (-40 °C to +100 °C) | — |
| Core Supply Voltage (VCCINT) | 2.5 V | 2.5 V (2.375 V to 2.625 V) |
| I/O Supply Voltage (VCCIO) | 3.3 V / 2.5 V / 1.8 V (per bank) | [DATA_NEEDED: VCCIO range] |
| Process Technology | 0.18 µm CMOS, SRAM-based | SRAM-based, 0.18 µm |
| Maximum Internal Frequency | up to 833 MHz (per family) | — |
| Configuration Mode | JTAG (IEEE 1149.1), passive serial, passive parallel asynchronous | — |
| Supported I/O Standards | LVTTL, LVCMOS, PCI | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS compliance] |
| Logic Elements (LEs) | — | 2,880 |
| Typical Gates | — | 50,000 |
| Maximum User I/O | — | 102 |
| Logic Array Blocks (LABs) | — | 360 |
| Total RAM Bits | — | 40,960 |
| Betriebstemperatur | — | -40 °C to +85 °C (Industrial) |
| Configuration Method | — | Passive Serial / Passive Parallel / JTAG |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |