EP1S20F672C6 vs EP1S20F672C7N Vergleich
Detaillierter Direktvergleich von EP1S20F672C6 von Altera und EP1S20F672C7N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1S20F672C6 | EP1S20F672C7N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $470,00 | $109,20 |
| Manufacturer | Altera (now Intel) | — |
| Series | Stratix | Stratix (first generation) |
| Family | Stratix (first generation) | Stratix |
| Process Technology | 0.13 µm CMOS | 130 nm CMOS |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Logic Array Blocks (LABs) | 1,846 | — |
| Embedded Memory Bits | 1,669,248 | — |
| Maximum User I/Os | 426 | — |
| Gehäuse | 672-ball FineLine BGA | 672-FBGA (FineLine BGA) |
| Package Code | F672 | — |
| Speed Grade | C6 | C7 (-7) |
| Betriebstemperatur | 0°C to +85°C (Commercial) | 0°C to +85°C (commercial) |
| Versorgungsspannung | Core 1.5 V, I/O programmable | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | — |
| Logic Cells | — | 18,460 |
| Configurable Logic Blocks (CLBs) | — | 2,132 |
| Embedded Memory (TriMatrix) | — | 1,669,248 bits (426 Kbit total) |
| DSP Blocks | — | 56 (dedicated 18x18 multipliers) |
| Maximum User I/O | — | 586 |
| I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| PLLs | — | Up to 12 |
| Maximum Operating Frequency | — | 420.17 MHz |
| Core Voltage | — | 1.5 V |
| Package Body Size | — | 35 mm x 35 mm |
| Ball Pitch | — | 1.27 mm |
| Lead-Free / RoHS | — | Yes (lead-free finish, RoHS compliant) |
| Configuration Modes | — | PS, PPS, FPP, JTAG |
| MSL-Level | — | [DATA_NEEDED: moisture sensitivity level] |