EP1S25F672C7 vs EP1S25F672C5N Vergleich
Detaillierter Direktvergleich von EP1S25F672C7 von Intel und EP1S25F672C5N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP1S25F672C7 - 25K LE Stratix FPGA, 672-BGA, 420 MHz | Intel
EP1S25F672C7 ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EP1S25F672C7 | EP1S25F672C5N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $595,00 | $142,00 |
| Series | Stratix | EP1S25 |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements (LEs) | 25,660 | — |
| Total RAM Bits | 1,944,576 | — |
| Configurable Logic Blocks (CLBs) | 2,852 | — |
| User I/O Count | 473 | — |
| Gehäuse | 672-BBGA (FBGA), 35 x 35 mm, 1.27 mm pitch | — |
| Core Voltage | 1.5 V | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Maximum Core Frequency | 420 MHz | — |
| Speed Grade | C7 (-7 commercial) | C5 |
| Betriebstemperatur | 0 °C to +85 °C (commercial) | — |
| Embedded Multipliers (18x18) | 224 | — |
| TriMatrix Memory Blocks | Yes (MRAM / M512 / M4K) | — |
| DLLs | 6 | — |
| PLLs | 2 | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | Compliant |
| Family | — | Stratix |
| Logic Elements (Cells) | — | 25,660 |
| Number of CLBs | — | 2,566 |
| Number of Logic Cells / Gates | — | [DATA_NEEDED: total system gates] |
| Maximum Internal Frequency | — | 500 MHz |
| Core Supply Voltage | — | 1.5 V (nominal) |
| Number of I/O Pins | — | 473 user I/O |
| Number of I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| Package Type | — | FineLine BGA (FBGA) |
| Package Pin Count | — | 672 |
| Ball Pitch | — | 1.00 mm |
| Betriebstemperaturbereich | — | 0 °C to +85 °C (commercial) |
| Lead-Free (Pb-Free) | — | Yes (suffix "N") |
| Configuration Method | — | SRAM-based, programmable via JTAG / Passive Serial / Fast Passive Parallel |