EP1S25F672C7N vs EP1S20B672C7N Vergleich
Detaillierter Direktvergleich von EP1S25F672C7N von Altera und EP1S20B672C7N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1S25F672C7N | EP1S20B672C7N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $535,00 | $320,00 |
| Device Family | Stratix | — |
| Logic Elements (LEs) | 25,660 | 18,460 |
| Logic Array Blocks (LABs) | 2,566 | — |
| Embedded Memory Bits | 1,944,576 | 1,669,248 bits |
| Maximum User I/O | 473 | 426 |
| Number of I/O Pins | 672 (BGA balls) | — |
| Gehäuse | 672-BBGA (FineLine BGA), 35 × 35 mm, 1.27 mm pitch | — |
| Process Technology | 0.13 µm CMOS | 0.13 µm CMOS |
| Core Supply Voltage (VCCINT) | 1.5 V | — |
| I/O Supply Voltage (VCCIO) | [DATA_NEEDED: bank-dependent 1.2 V–3.3 V] | — |
| Betriebstemperatur | 0 °C to 85 °C (commercial) | 0 °C to 85 °C (Commercial Extended) |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Configuration Method | JTAG / Passive Serial / Active Serial | — |
| MSL-Level | [DATA_NEEDED: MSL rating] | 3 (per JEDEC J-STD-020) |
| RoHS-Status | [DATA_NEEDED: confirm from product page] | [DATA_NEEDED: RoHS compliance] |
| Series | — | Stratix |
| Family | — | Stratix (original) |
| LABs / CLBs | — | 1,846 |
| Number of Pins / Balls | — | 672 |
| Package Type | — | 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch) |
| Supply Voltage (Core, VCCINT) | — | 1.5 V |
| Speed Grade | — | -7 |
| Logic Family | — | CMOS |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |