EP1S25F672C7N vs EP1S25F672C5N Vergleich
Detaillierter Direktvergleich von EP1S25F672C7N von Altera und EP1S25F672C5N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1S25F672C7N | EP1S25F672C5N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $535,00 | $142,00 |
| Device Family | Stratix | — |
| Logic Elements (LEs) | 25,660 | — |
| Logic Array Blocks (LABs) | 2,566 | — |
| Embedded Memory Bits | 1,944,576 | — |
| Maximum User I/O | 473 | — |
| Number of I/O Pins | 672 (BGA balls) | 473 user I/O |
| Gehäuse | 672-BBGA (FineLine BGA), 35 × 35 mm, 1.27 mm pitch | — |
| Process Technology | 0.13 µm CMOS | 130 nm CMOS |
| Core Supply Voltage (VCCINT) | 1.5 V | — |
| I/O Supply Voltage (VCCIO) | [DATA_NEEDED: bank-dependent 1.2 V–3.3 V] | — |
| Betriebstemperatur | 0 °C to 85 °C (commercial) | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Configuration Method | JTAG / Passive Serial / Active Serial | SRAM-based, programmable via JTAG / Passive Serial / Fast Passive Parallel |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| RoHS-Status | [DATA_NEEDED: confirm from product page] | Compliant |
| Family | — | Stratix |
| Series | — | EP1S25 |
| Logic Elements (Cells) | — | 25,660 |
| Number of CLBs | — | 2,566 |
| Number of Logic Cells / Gates | — | [DATA_NEEDED: total system gates] |
| Maximum Internal Frequency | — | 500 MHz |
| Core Supply Voltage | — | 1.5 V (nominal) |
| Number of I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| Package Type | — | FineLine BGA (FBGA) |
| Package Pin Count | — | 672 |
| Ball Pitch | — | 1.00 mm |
| Betriebstemperaturbereich | — | 0 °C to +85 °C (commercial) |
| Speed Grade | — | C5 |
| Lead-Free (Pb-Free) | — | Yes (suffix "N") |