EP1S60F1020C6N vs EP1S60F1020C6NAA Vergleich
Detaillierter Direktvergleich von EP1S60F1020C6N von Intel und EP1S60F1020C6NAA von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1S60F1020C6N | EP1S60F1020C6NAA |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $195,00 | $145,00 |
| Series | Stratix | EP1S60 |
| Family | Stratix (EP1S) | Stratix |
| Logic Elements (LEs) | 57,120 | — |
| Logic Cells | 6,570 blocks (per chipdig datasheet summary) | — |
| Embedded RAM (Total Bits) | 5,215,104 bits | — |
| Embedded Multipliers | 773 (18x18) | 192 (18x18) |
| Maximum User I/O Pins | Per datasheet, package-dependent (F1020 variant) | 773 |
| Package Type | 1020-ball FBGA (FineLine BGA), 33 x 33 mm, 1 mm pitch | — |
| Logic Family / Process | CMOS, 0.13 µm | — |
| Betriebstemperatur | 0°C to +85°C (Commercial) | 0C to +85C (commercial) |
| Versorgungsspannung | Per datasheet (Stratix Device Handbook Vol. 1) | — |
| Speed Grade | C6 (mid-tier) | C6 |
| Lead-Free / Pb-Free | Yes (suffix 'N') | — |
| RoHS-Status | Compliant (per 'N' suffix) | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| Configuration | JTAG / Passive Serial / Fast Passive Parallel via MSEL pins | — |
| PLL Count | 12 (per Stratix family datasheet) | — |
| Memory Block Types | TriMatrix (M512, M4K, M-RAM) | — |
| Logic Elements | — | 57,120 |
| Total RAM Bits | — | 5,215,104 |
| Number of LABs/CLBs | — | 4,510 |
| Number of Logic Cells | — | 57,120 |
| Gehäuse | — | 1020-BBGA (FineLine BGA), 33x33 mm, 1.0 mm pitch |
| Process Node | — | 0.13 µm CMOS |
| Voltage - Core | — | 1.5 V |
| Voltage - I/O | — | 1.5V / 1.8V / 2.5V / 3.3V (MultiVolt) |
| Lead-Free / RoHS | — | Yes (N suffix) |
| Configuration Scheme | — | Passive Serial / Fast Passive Parallel / JTAG |
| Number of PLLs | — | 12 |
| Global Clocks | — | 40 |