EP1S80F1020C6 vs EP1S60F1020C6N Vergleich
Detaillierter Direktvergleich von EP1S80F1020C6 von Intel und EP1S60F1020C6N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1S80F1020C6 | EP1S60F1020C6N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1.180,00 | $195,00 |
| Series | Stratix | Stratix |
| Logic Elements | 79,040 | — |
| Total RAM Bits | 7,427,520 | — |
| Number of Logic Blocks / LABs | 9,191 | — |
| Number of I/O Pins (max) | 773 user I/O | — |
| Number of Pins / Balls | 1020 | — |
| Package Type | FC-FBGA (flip-chip fine-pitch BGA), 33 x 33 mm, 1.0 mm pitch | 1020-ball FBGA (FineLine BGA), 33 x 33 mm, 1 mm pitch |
| Process Technology | 130 nm CMOS | — |
| Core Supply Voltage (VCCINT) | 1.5 V nominal (1.425 V to 1.575 V) | — |
| Speed Grade | C6 | C6 (mid-tier) |
| Operating Temperature (Commercial) | 0 C to +85 C | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Maximum Internal Clock Frequency | 450.05 MHz | — |
| Family Description | FPGA - Field Programmable Gate Array | — |
| Embedded Memory | TriMatrix (three block sizes, true/simple dual-port) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + serial/parallel configuration device | — |
| Design Tool | Quartus II (legacy, Stratix family) | — |
| RoHS-Status | [DATA_NEEDED: rohs status] | Compliant (per 'N' suffix) |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | [DATA_NEEDED: MSL rating] | — |
| Family | — | Stratix (EP1S) |
| Logic Elements (LEs) | — | 57,120 |
| Logic Cells | — | 6,570 blocks (per chipdig datasheet summary) |
| Embedded RAM (Total Bits) | — | 5,215,104 bits |
| Embedded Multipliers | — | 773 (18x18) |
| Maximum User I/O Pins | — | Per datasheet, package-dependent (F1020 variant) |
| Logic Family / Process | — | CMOS, 0.13 µm |
| Betriebstemperatur | — | 0°C to +85°C (Commercial) |
| Versorgungsspannung | — | Per datasheet (Stratix Device Handbook Vol. 1) |
| Lead-Free / Pb-Free | — | Yes (suffix 'N') |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |
| Configuration | — | JTAG / Passive Serial / Fast Passive Parallel via MSEL pins |
| PLL Count | — | 12 (per Stratix family datasheet) |
| Memory Block Types | — | TriMatrix (M512, M4K, M-RAM) |