EP1S80F1020I7N vs EP1S80F1020C5N Vergleich
Detaillierter Direktvergleich von EP1S80F1020I7N von Altera und EP1S80F1020C5N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP1S80F1020I7N - Stratix 79K LEs 1020-BGA FPGA | Altera
EP1S80F1020I7N ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EP1S80F1020I7N | EP1S80F1020C5N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Ende des Lebenszyklus |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $6.500,00 | $0,00 |
| Family | Stratix | — |
| Logic Elements | 79,040 | 79,040 |
| Adaptive Logic Modules (ALMs) | 7,904 LABs/CLBs | — |
| Total RAM Bits | 7,427,520 | — |
| User I/O Count | 773 | — |
| Core Voltage | 1.5 V | — |
| Process Technology | 130 nm | — |
| Gehäuse | 1020-ball FC-FBGA | — |
| Maximum Operating Frequency | 420.17 MHz | — |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Operating Temperature Grade | Industrial (-40C to +100C) | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | unknown |
| MSL-Level | 3 | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Product Type | — | Field Programmable Gate Array (FPGA) |
| Device Family | — | Stratix |
| Logic Technology | — | CMOS |
| Logic Cells | — | 9,191 |
| Logic Array Blocks | — | 7,904 |
| User I/O Pins | — | 773 I/O |
| Total Package Pins or Balls | — | 1,020 |
| Package Type | — | FBGA-1020 |
| Package Dimensions | — | 33 mm x 33 mm |
| Ball Pitch | — | 1 mm |
| Betriebstemperatur | — | 0 °C to 85 °C |
| Versorgungsspannung | — | [DATA_NEEDED: operating supply voltage] |
| Speed Grade | — | C5 |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | not_applicable |
| Embedded Memory Capacity | — | [DATA_NEEDED: embedded memory capacity] |
| Phase-Locked Loops | — | [DATA_NEEDED: PLL count] |
| Transceiver Count | — | [DATA_NEEDED: transceiver count] |