EP1SGX25FF1020I5 vs EP1SGX25FF1020 Vergleich

Detaillierter Direktvergleich von EP1SGX25FF1020I5 von Altera und EP1SGX25FF1020 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Altera
EP1SGX25FF1020I5 EP1SGX25FF1020I5 - Stratix GX FPGA, 25.6K Logic Cells | Intel / Altera

EP1SGX25FF1020I5 - Stratix GX FPGA, 25.6K Logic Cells | Intel / Altera

EP1SGX25FF1020I5 ⚠ Letzte Bestellmöglichkeit

Spezifikationsvergleich

Parameter EP1SGX25FF1020I5 EP1SGX25FF1020
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Letzte Kaufgelegenheit Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $1.490,00 $295,00
Family Stratix GX Stratix GX
Logic Cells 25,660 —
Configurable Logic Blocks (CLBs) 2,566 —
Maximum Internal Performance 5000 MHz —
Process Technology 130 nm CMOS 130 nm CMOS
Core Supply Voltage (Nominal) 1.5 V —
Core Supply Voltage Range 1.425 V to 1.575 V —
Gehäuse 1020-ball FC-FBGA (FF1020) 1020-ball FCBGA (PBGA, 1.00 mm pitch)
Terminal Form Ball —
Number of Terminals 1020 —
Temperature Grade (suffix I5) Industrial —
Combinatorial Delay (ES variant) 7.49 ns max —
Montageart Surface Mount (Flip-Chip BGA) Surface Mount (BGA)
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Embedded Transceivers Present (Stratix GX family) —
Logic Elements (LE) — 25,660
Configurable Logic Blocks (CLB) — 2,566
Embedded Memory (bits) — 1,944,576
Logic Cells (per FPGAkey) — 25,660
Combinatorial Delay (Tpd) — 7.49 ns (per Microchip USA datasheet summary)
Operating Frequency (max) — [DATA_NEEDED: max internal operating frequency]
Pin/Package Count — 1020
Betriebstemperatur — -40C to +85C (industrial variant) / 0C to +85C (commercial variant)
Versorgungsspannung — [DATA_NEEDED: core VCC voltage]
Serial Transceivers — Embedded SERDES (multi-gigabit, protocol-dependent)
DSP Blocks — Embedded dedicated multipliers
PLL / Clock Management — Embedded PLLs
Configuration Method — SRAM-based, configuration via JTAG / passive serial / fast passive parallel

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern