EP1SGX40CF1020I5 vs EP1SGX40DF1020I7 Vergleich
Detaillierter Direktvergleich von EP1SGX40CF1020I5 von Altera und EP1SGX40DF1020I7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP1SGX40DF1020I7 - 41,250 LEs Stratix GX FPGA, 1.5V FC-FBGA-1020 | Altera
EP1SGX40DF1020I7 ObsoleteSpezifikationsvergleich
| Parameter | EP1SGX40CF1020I5 | EP1SGX40DF1020I7 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $370,00 | $188,00 |
| Series | Stratix GX | — |
| Family | Stratix (first generation) | Stratix GX |
| Logic Elements | 41,250 | 41,250 |
| Configurable Logic Blocks (CLBs) | 4,125 | 4,125 |
| Total RAM Bits | 3,423,744 | — |
| Number of Logic Cells / Gates | [DATA_NEEDED: gate count equivalent] | — |
| Process Technology | CMOS | 130 nm CMOS |
| Supply Voltage (Core) | 1.5 V | — |
| Number of Transceivers | 624 (per DigiKey listing family variant) | — |
| Number of I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Package Type | FBGA-1020 (FineLine BGA) | — |
| Package Dimensions | 33 mm x 33 mm | — |
| Ball Pitch | 1.0 mm | — |
| Betriebstemperatur | -40C to +100C (industrial, I suffix) | -40 °C to +100 °C (I7 grade per family datasheet) |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: confirmed RoHS per Intel/Altera] | [DATA_NEEDED: RoHS status] |
| Configuration Memory | SRAM-based (external config device required) | — |
| Speed Grade | 5 | — |
| Device Family Suffix Decoding | C = standard logic, F = enhanced, I = industrial temp | — |
| Nominal Core Supply Voltage | — | 1.5 V |
| Supply Voltage Range | — | 1.425 V to 1.575 V |
| Gehäuse | — | 1020-ball FC-FBGA |
| Terminal Form | — | Ball |
| Package Shape | — | Square |
| Grading of Temperature | — | Military (I7 grade) |
| Technology | — | CMOS |
| Combinatorial CLB Delay | — | 9.48 ns (per family datasheet) |