EP1SGX40DF1020C6 vs EP1SGX40DF1020C5ES Vergleich
Detaillierter Direktvergleich von EP1SGX40DF1020C6 von Altera und EP1SGX40DF1020C5ES von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP1SGX40DF1020C6 - Stratix GX 41,250 Cells FPGA, 624 I/O | Altera
EP1SGX40DF1020C6 ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EP1SGX40DF1020C6 | EP1SGX40DF1020C5ES |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1.620,00 | $0,00 |
| Series | Stratix GX | — |
| Family | Stratix GX FPGA | — |
| Manufacturer | Altera (Intel) | — |
| Logic Cells | 41,250 | 41,250 cells |
| Number of LABs/CLBs | 4,125 | — |
| Total RAM Bits | [DATA_NEEDED: total RAM bits] | — |
| Number of I/O | 624 | — |
| Voltage - Supply | 1.425 V to 1.575 V (1.5 V nominal) | — |
| Betriebstemperatur | 0C to +85C (commercial) | 0 C to 85 C |
| Gehäuse / Bauform | 1020-BBGA, FCBGA (FC-FBGA) | — |
| Supplier Device Package | 1020-FBGA (33 x 33 mm, 1 mm pitch) | — |
| Montageart | Surface Mount | — |
| Process Technology | 130 nm CMOS | 130 nm |
| Maximum Internal Performance | 5000 MHz (per datasheet rating) | — |
| Logic Family | CMOS, SRAM-based configuration | Stratix GX |
| Programmable Type | In-System Programmable (SRAM) | — |
| High-Speed Transceivers | Embedded (per Stratix GX family) | — |
| Configuration Modes | JTAG, Passive Serial, Fast Passive Parallel, Active Serial | — |
| Packaging | Bulk / Tray | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | unknown |
| Product Type | — | Field-Programmable Gate Array (FPGA) |
| Logic Technology | — | CMOS |
| Logic Array Blocks | — | 4,125 LABs |
| Configurable I/O Connections | — | 624 input and 624 output connections |
| Versorgungsspannung | — | 1.5 V |
| Reported Maximum Frequency | — | 5,000 MHz |
| Reported Maximum CLB Combinatorial Delay | — | 7.49 ns |
| Alternative Listed Maximum Clock Frequency | — | 6 MHz |
| Terminal Count | — | 1,020 pins |
| Package Type | — | FC-FBGA-1020 |
| Package Dimensions | — | 33 mm x 33 mm |
| Ball Pitch | — | 1 mm |
| Mounting Configuration | — | Surface-mount ball grid array |
| Terminal Form | — | Ball |
| Package Code | — | BGA |
| Configuration Method | — | [DATA_NEEDED: configuration method] |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | unknown |