EP1SGX40DF1020C6 vs EP1SGX40G Vergleich

Detaillierter Direktvergleich von EP1SGX40DF1020C6 von Altera und EP1SGX40G von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Altera
EP1SGX40DF1020C6 EP1SGX40DF1020C6 - Stratix GX 41,250 Cells FPGA, 624 I/O | Altera

EP1SGX40DF1020C6 - Stratix GX 41,250 Cells FPGA, 624 I/O | Altera

EP1SGX40DF1020C6 ⚠ Letzte Bestellmöglichkeit

Spezifikationsvergleich

Parameter EP1SGX40DF1020C6 EP1SGX40G
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Letzte Kaufgelegenheit Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $1.620,00 $595,00
Series Stratix GX —
Family Stratix GX FPGA Stratix GX
Manufacturer Altera (Intel) —
Logic Cells 41,250 —
Number of LABs/CLBs 4,125 —
Total RAM Bits [DATA_NEEDED: total RAM bits] 3,423,744
Number of I/O 624 —
Voltage - Supply 1.425 V to 1.575 V (1.5 V nominal) —
Betriebstemperatur 0C to +85C (commercial) —
Gehäuse / Bauform 1020-BBGA, FCBGA (FC-FBGA) —
Supplier Device Package 1020-FBGA (33 x 33 mm, 1 mm pitch) —
Montageart Surface Mount —
Process Technology 130 nm CMOS [DATA_NEEDED: process node]
Maximum Internal Performance 5000 MHz (per datasheet rating) —
Logic Family CMOS, SRAM-based configuration —
Programmable Type In-System Programmable (SRAM) —
High-Speed Transceivers Embedded (per Stratix GX family) —
Configuration Modes JTAG, Passive Serial, Fast Passive Parallel, Active Serial —
Packaging Bulk / Tray —
RoHS-Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance]
Logic Elements — 41,250
DSP Blocks — [DATA_NEEDED: DSP block count]
Maximum User I/O Pins — 624
Gehäuse — 1020-pin FineLine BGA
Number of Transceivers — 20
Maximum Transceiver Data Rate — 3.1875 Gbps
Minimum Transceiver Data Rate — 500 Mbps
Transceiver Channels per Bank — 4
Supported Serial Standards — PCI Express, XAUI, Serial RapidIO, SerialLite II
8B/10B Encoder/Decoder — Hardware (dedicated per channel)
PLLs — [DATA_NEEDED: PLL count]
Speed Grades Available — C5, C6, C7, I5, I6, I7
Operating Temperature Range (Commercial) — 0C to +85C
Operating Temperature Range (Industrial) — -40C to +100C
Configuration Method — EPC enhanced configuration devices, JTAG
Vertical Migration — Supported within 1020-pin FineLine BGA package (EP1SGX25/EP1SGX40)

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