EP20K1000CF672C8ES vs EP20K1000CF672C7 Vergleich
Detaillierter Direktvergleich von EP20K1000CF672C8ES von Intel und EP20K1000CF672C7 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP20K1000CF672C8ES - 1M-gate APEX20KE FPGA, 672-BGA | Intel
EP20K1000CF672C8ES ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP20K1000CF672C8ES | EP20K1000CF672C7 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $285,00 | $158,00 |
| Family | APEX 20K (APEX20KE) | APEX 20KC |
| Logic Elements | 38,400 | — |
| Typical Gates | 25,920 | — |
| Maximum System Gates | 1,000,000 | — |
| Embedded Memory (ESB) | 216 Kbits | — |
| User I/O Pins | 508 | — |
| Gehäuse | 672-ball FineLine BGA | 672-ball FC-FBGA (45 × 45 mm, 1.27 mm pitch) |
| Speed Grade | C8 | C7 (fastest) |
| Betriebstemperatur | Commercial (0C to +85C) | 0 °C to +85 °C (commercial, C suffix) |
| Process Technology | 0.18 µm CMOS | 0.15 µm all-layer copper CMOS |
| Core Voltage (VCCINT) | 2.5 V | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, LVDS, LVPECL, GTL, SSTL-2/3 | — |
| PLLs | 4 (ClockLock/ClockBoost) | — |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) | — |
| MSL-Level | 3 (168 hours) | [DATA_NEEDED: moisture sensitivity level] |
| Montageart | Surface Mount (BGA) | Surface Mount |
| RoHS-Status | Compliant | [DATA_NEEDED: RoHS status - part predates common RoHS reporting] |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| System Gates | — | 1,000,000 (typical) |
| Logic Elements / Cells | — | 38400 |
| Maximum Internal Frequency | — | 375.94 MHz |
| Propagation Delay | — | 1.6 ns (typical) |
| Core Supply Voltage | — | 1.8 V |
| User I/O Count | — | 488 (some sources list 508) |
| Embedded Memory (EAB) | — | Embedded array blocks (RAM/CAM/ROM) |
| PLL Count | — | 4 |
| Configuration Interface | — | Passive Serial, JTAG (IEEE 1149.1), Fast Passive Parallel |