EP20K100CT144C7ES vs EP20K100CT144C9 Vergleich
Detaillierter Direktvergleich von EP20K100CT144C7ES von Altera und EP20K100CT144C9 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K100CT144C7ES - APEX-20K 100K Gate FPGA, 93 I/O, 144-LQFP | Altera
EP20K100CT144C7ES NrndSpezifikationsvergleich
| Parameter | EP20K100CT144C7ES | EP20K100CT144C9 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $64,00 | $18,75 |
| Series | APEX-20K | — |
| Core Voltage (VCCINT) | 2.375 V to 2.625 V | 2.5 V |
| Typical Gate Count | 100,000 gates | — |
| Logic Elements | 4,160 | — |
| Total RAM Bits | 53,248 bits | — |
| User I/O Pins | 93 | — |
| Gehäuse | 144-LQFP (20x20 mm) | 144-LQFP |
| Betriebstemperatur | 0C to +85C (Commercial) | 0C to +85C (Commercial) |
| Process Technology | 0.18 µm CMOS | 0.22 um CMOS |
| Montageart | Surface Mount | Surface Mount |
| MultiVolt I/O Levels | 1.8 V, 2.5 V, 3.3 V, 5 V | — |
| Configuration Interface | IEEE 1149.1 JTAG | — |
| MSL-Level | 3 | — |
| RoHS-Status | Compliant (per Besenchips listing) | [DATA_NEEDED: rohs status] |
| Lead-Free | Yes | — |
| Family | — | APEX-20K |
| Device Logic Elements | — | 4,160 |
| Typical Gates | — | 100,000 |
| Embedded Memory (RAM bits) | — | 53,248 |
| Maximum User I/O | — | 93 |
| Speed Grade | — | -9 |
| I/O Voltage (VCCIO) | — | 3.3 V |
| Number of PLLs | — | 4 |
| Configuration Method | — | SRAM / JTAG (IEEE 1149.1) |