EP20K100EBC356-3N vs EP20K100EBC652-2X Vergleich
Detaillierter Direktvergleich von EP20K100EBC356-3N von Altera und EP20K100EBC652-2X von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K100EBC356-3N | EP20K100EBC652-2X |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $92,00 | $85,00 |
| Series | APEX-20KE | — |
| Family | APEX 20K | APEX 20KE |
| Logic Elements / Cells | 4160 | — |
| System Gates | 100,000 | — |
| Embedded Memory (bits) | 53,248 | — |
| Embedded System Blocks (ESBs) | 26 | 26 |
| Maximum User I/Os | 246 | — |
| Anzahl der Pins | 356 | — |
| Gehäuse | 356-LBGA (Ball Grid Array) | 652-ball BGA (EBC652) |
| Package Dimensions | 45 x 45 mm | — |
| Ball Pitch | 1.27 mm | — |
| Process Technology | 0.22 µm CMOS | 0.18 µm CMOS, SRAM-based |
| Core Supply Voltage | 1.8 V | — |
| Propagation Delay | 1.6 ns (speed grade -3N) | — |
| Maximum Internal Frequency | 250 MHz | — |
| Betriebstemperatur | 0 °C to +85 °C | 0C to +85C (commercial) |
| Montageart | Surface Mount | Surface Mount |
| Programmable Interface | JTAG (IEEE 1149.1) | — |
| I/O Standards Supported | LVCMOS, LVTTL, PCI, SSTL-2/3, GTL+ | — |
| RoHS-Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status] |
| Typical Gates | — | 100,000 |
| Maximum System Gates | — | 263,000 |
| Logic Elements | — | 4,160 |
| Maximum RAM Bits | — | 53,248 |
| Maximum User I/O Pins | — | 246 |
| Supply Voltage - Core | — | 1.8 V |
| Supply Voltage - I/O | — | 1.8 V / 2.5 V / 3.3 V |
| Speed Grade | — | -2 (faster commercial) |
| Configuration Method | — | Passive Serial / Passive Parallel / JTAG (EPC) |
| Clock Resources | — | Up to 4 DLLs, multiple global clocks |