EP20K100EBC652-2X vs EP20K100EFC144-1 Vergleich
Detaillierter Direktvergleich von EP20K100EBC652-2X von Altera und EP20K100EFC144-1 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K100EBC652-2X | EP20K100EFC144-1 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $85,00 | $61,75 |
| Family | APEX 20KE | — |
| Typical Gates | 100,000 | 100,000 |
| Maximum System Gates | 263,000 | 263,000 |
| Logic Elements | 4,160 | 4,160 |
| Embedded System Blocks (ESBs) | 26 | Yes (memory + dedicated logic) |
| Maximum RAM Bits | 53,248 | — |
| Maximum User I/O Pins | 246 | — |
| Supply Voltage - Core | 1.8 V | — |
| Supply Voltage - I/O | 1.8 V / 2.5 V / 3.3 V | — |
| Gehäuse | 652-ball BGA (EBC652) | — |
| Speed Grade | -2 (faster commercial) | — |
| Process Technology | 0.18 µm CMOS, SRAM-based | 0.15-µm all-layer copper |
| Betriebstemperatur | 0C to +85C (commercial) | 0 °C to 85 °C (commercial) |
| Montageart | Surface Mount | Surface Mount |
| Configuration Method | Passive Serial / Passive Parallel / JTAG (EPC) | SRAM (volatile) - external boot PROM required |
| Clock Resources | Up to 4 DLLs, multiple global clocks | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | APEX 20KE |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| User I/Os | — | 93 |
| Propagation Delay | — | 1.6 ns |
| PLLs | — | 4 |
| Package Type | — | 144-ball FBGA (13x13 mm, 1.0 mm pitch) |
| Core Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Voltage Support | — | 1.8 V / 2.5 V / 3.3 V (multiVolt I/O) |
| Boundary-Scan Support | — | IEEE 1149.1 (JTAG) |